P0 = R2;
P1 = R1;
CSYNC;
- 1:
+1:
IFLUSH[P0++];
CC = P0 < P1(iu);
IF CC JUMP 1b(bp);
P0.H = (IMEM_CONTROL >> 16);
R7 =[P0];
-/*
- * Clear the IMC bit , All valid bits in the instruction
- * cache are set to the invalid state
- */
+ /*
+ * Clear the IMC bit , All valid bits in the instruction
+ * cache are set to the invalid state
+ */
BITCLR(R7, IMC_P);
CLI R6;
/* SSYNC required before invalidating cache. */
(R7:5) =[SP++];
RTS;
-/*
+/*
* Invalidate the Entire Data cache by
* clearing DMC[1:0] bits
*/
P0.H = (DMEM_CONTROL >> 16);
R7 =[P0];
-/*
- * Clear the DMC[1:0] bits, All valid bits in the data
- * cache are set to the invalid state
- */
+ /*
+ * Clear the DMC[1:0] bits, All valid bits in the data
+ * cache are set to the invalid state
+ */
BITCLR(R7, DMC0_P);
BITCLR(R7, DMC1_P);
CLI R6;
CC = P0 < P1(iu);
IF CC JUMP 1b(bp);
-/*
- * If the data crosses a cache line, then we'll be pointing to
- * the last cache line, but won't have flushed/invalidated it yet, so do
- * one more.
- */
+ /*
+ * If the data crosses a cache line, then we'll be pointing to
+ * the last cache line, but won't have flushed/invalidated it yet, so do
+ * one more.
+ */
FLUSHINV[P0];
SSYNC;
RTS;