Merge ../u-boot

[oweals/u-boot.git] / cpu / bf533 / cache.S

diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S
index 5dcc24fd52f6843e7b34efb4a725eb012d934b68..03aebe4b4c596a828d70263280b62acecbbf0225 100644 (file)
--- a/cpu/bf533/cache.S
+++ b/cpu/bf533/cache.S
@@ -11,7 +11,7 @@ ENTRY(_blackfin_icache_flush_range)
        P0 = R2;
        P1 = R1;
        CSYNC;
-       1:
+1:
        IFLUSH[P0++];
        CC = P0 < P1(iu);
        IF CC JUMP 1b(bp);
@@ -41,10 +41,10 @@ ENTRY(_invalidate_entire_icache)
        P0.H = (IMEM_CONTROL >> 16);
        R7 =[P0];
 
-/*
- * Clear the IMC bit , All valid bits in the instruction
- * cache are set to the invalid state
- */
+       /*
+        * Clear the IMC bit , All valid bits in the instruction
+        * cache are set to the invalid state
+        */
        BITCLR(R7, IMC_P);
        CLI R6;
        /* SSYNC required before invalidating cache. */
@@ -80,10 +80,10 @@ ENTRY(_dcache_invalidate)
        P0.H = (DMEM_CONTROL >> 16);
        R7 =[P0];
 
-/*
- * Clear the DMC[1:0] bits, All valid bits in the data
- * cache are set to the invalid state
- */
+       /*
+        * Clear the DMC[1:0] bits, All valid bits in the data
+        * cache are set to the invalid state
+        */
        BITCLR(R7, DMC0_P);
        BITCLR(R7, DMC1_P);
        CLI R6;
@@ -118,11 +118,11 @@ ENTRY(_blackfin_dcache_invalidate_range)
        CC = P0 < P1(iu);
        IF CC JUMP 1b(bp);
 
-/*
- * If the data crosses a cache line, then we'll be pointing to
- * the last cache line, but won't have flushed/invalidated it yet, so do
- * one more.
- */
+       /*
+        * If the data crosses a cache line, then we'll be pointing to
+        * the last cache line, but won't have flushed/invalidated it yet, so do
+        * one more.
+        */
        FLUSHINV[P0];
        SSYNC;
        RTS;