* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
static void cache_flush(void);
-static void cp_delay(void)
-{
- /* Many OMAP regs need at least 2 nops */
- asm("nop");
- asm("nop");
-}
-
int cpu_init(void)
{
/*
return 0;
}
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- disable_interrupts();
- reset_cpu(0);
-
- /* NOTREACHED */
- return 0;
-}
-
-void icache_enable(void)
-{
- ulong reg;
-
- reg = get_cr(); /* get control reg. */
- cp_delay();
- set_cr(reg | CR_I);
-}
-
-void icache_disable(void)
-{
- ulong reg;
-
- reg = get_cr();
- cp_delay();
- set_cr(reg & ~CR_I);
-}
-
-void dcache_disable (void)
-{
- ulong reg;
-
- reg = get_cr ();
- cp_delay ();
- set_cr (reg & ~CR_C);
-}
-
void l2cache_enable()
{
unsigned long i;
volatile unsigned int j;
/* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() == CPU_3430_ES2) {
+ if (get_cpu_rev() >= CPU_3XX_ES20) {
__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
volatile unsigned int j;
/* ES2 onwards we can disable/enable L2 ourselves */
- if (get_cpu_rev() == CPU_3430_ES2) {
+ if (get_cpu_rev() >= CPU_3XX_ES20) {
__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
}
}
-int icache_status(void)
-{
- return (get_cr() & CR_I) != 0;
-}
-
static void cache_flush(void)
{
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));