arm: unify interrupt init

[oweals/u-boot.git] / cpu / arm_cortexa8 / cpu.c

diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 506dbec173201da98b3fcfc8c63b76a159f17620..b91cc4f3b3e4ee4d27f477242986b694f61409e9 100644 (file)
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -6,7 +6,7 @@
  * Marius Groeger <mgroeger@sysgo.de>
  *
  * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -36,33 +36,14 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 #ifndef CONFIG_L2_OFF
 void l2cache_disable(void);
 #endif
 
 static void cache_flush(void);
 
-static void cp_delay(void)
-{
-       /* Many OMAP regs need at least 2 nops */
-       asm("nop");
-       asm("nop");
-}
-
 int cpu_init(void)
 {
-       /*
-        * setup up stacks if necessary
-        */
-#ifdef CONFIG_USE_IRQ
-       IRQ_STACK_START =
-           _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-       FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
        return 0;
 }
 
@@ -102,49 +83,13 @@ int cleanup_before_linux(void)
        return 0;
 }
 
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-       disable_interrupts();
-       reset_cpu(0);
-
-       /* NOTREACHED */
-       return 0;
-}
-
-void icache_enable(void)
-{
-       ulong reg;
-
-       reg = get_cr(); /* get control reg. */
-       cp_delay();
-       set_cr(reg | CR_I);
-}
-
-void icache_disable(void)
-{
-       ulong reg;
-
-       reg = get_cr();
-       cp_delay();
-       set_cr(reg & ~CR_I);
-}
-
-void dcache_disable (void)
-{
-       ulong reg;
-
-       reg = get_cr ();
-       cp_delay ();
-       set_cr (reg & ~CR_C);
-}
-
 void l2cache_enable()
 {
        unsigned long i;
        volatile unsigned int j;
 
        /* ES2 onwards we can disable/enable L2 ourselves */
-       if (get_cpu_rev() == CPU_3430_ES2) {
+       if (get_cpu_rev() >= CPU_3XX_ES20) {
                __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
                __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
                __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
@@ -174,7 +119,7 @@ void l2cache_disable()
        volatile unsigned int j;
 
        /* ES2 onwards we can disable/enable L2 ourselves */
-       if (get_cpu_rev() == CPU_3430_ES2) {
+       if (get_cpu_rev() >= CPU_3XX_ES20) {
                __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
                __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
                __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
@@ -197,11 +142,6 @@ void l2cache_disable()
        }
 }
 
-int icache_status(void)
-{
-       return (get_cr() & CR_I) != 0;
-}
-
 static void cache_flush(void)
 {
        asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));