ppc/85xx: Fix crashes due to generation of SPE instruction

[oweals/u-boot.git] / cpu / arm_cortexa8 / cpu.c

diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 506dbec173201da98b3fcfc8c63b76a159f17620..a01e0d605ff8fc6397687cc6d7c8de9508143b21 100644 (file)
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -6,7 +6,7 @@
  * Marius Groeger <mgroeger@sysgo.de>
  *
  * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -33,39 +33,14 @@
 
 #include <common.h>
 #include <command.h>
-#include <asm/arch/sys_proto.h>
 #include <asm/system.h>
-
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
+#include <asm/cache.h>
 #ifndef CONFIG_L2_OFF
-void l2cache_disable(void);
+#include <asm/arch/sys_proto.h>
 #endif
 
 static void cache_flush(void);
 
-static void cp_delay(void)
-{
-       /* Many OMAP regs need at least 2 nops */
-       asm("nop");
-       asm("nop");
-}
-
-int cpu_init(void)
-{
-       /*
-        * setup up stacks if necessary
-        */
-#ifdef CONFIG_USE_IRQ
-       IRQ_STACK_START =
-           _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-       FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-       return 0;
-}
-
 int cleanup_before_linux(void)
 {
        unsigned int i;
@@ -87,121 +62,21 @@ int cleanup_before_linux(void)
 
 #ifndef CONFIG_L2_OFF
        /* turn off L2 cache */
-       l2cache_disable();
+       l2_cache_disable();
        /* invalidate L2 cache also */
-       v7_flush_dcache_all(get_device_type());
+       invalidate_dcache(get_device_type());
 #endif
        i = 0;
        /* mem barrier to sync up things */
        asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
 
 #ifndef CONFIG_L2_OFF
-       l2cache_enable();
+       l2_cache_enable();
 #endif
 
        return 0;
 }
 
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-       disable_interrupts();
-       reset_cpu(0);
-
-       /* NOTREACHED */
-       return 0;
-}
-
-void icache_enable(void)
-{
-       ulong reg;
-
-       reg = get_cr(); /* get control reg. */
-       cp_delay();
-       set_cr(reg | CR_I);
-}
-
-void icache_disable(void)
-{
-       ulong reg;
-
-       reg = get_cr();
-       cp_delay();
-       set_cr(reg & ~CR_I);
-}
-
-void dcache_disable (void)
-{
-       ulong reg;
-
-       reg = get_cr ();
-       cp_delay ();
-       set_cr (reg & ~CR_C);
-}
-
-void l2cache_enable()
-{
-       unsigned long i;
-       volatile unsigned int j;
-
-       /* ES2 onwards we can disable/enable L2 ourselves */
-       if (get_cpu_rev() == CPU_3430_ES2) {
-               __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
-               __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
-               __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
-       } else {
-               /* Save r0, r12 and restore them after usage */
-               __asm__ __volatile__("mov %0, r12":"=r"(j));
-               __asm__ __volatile__("mov %0, r0":"=r"(i));
-
-               /*
-                * GP Device ROM code API usage here
-                * r12 = AUXCR Write function and r0 value
-                */
-               __asm__ __volatile__("mov r12, #0x3");
-               __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
-               __asm__ __volatile__("orr r0, r0, #0x2");
-               /* SMI instruction to call ROM Code API */
-               __asm__ __volatile__(".word 0xE1600070");
-               __asm__ __volatile__("mov r0, %0":"=r"(i));
-               __asm__ __volatile__("mov r12, %0":"=r"(j));
-       }
-
-}
-
-void l2cache_disable()
-{
-       unsigned long i;
-       volatile unsigned int j;
-
-       /* ES2 onwards we can disable/enable L2 ourselves */
-       if (get_cpu_rev() == CPU_3430_ES2) {
-               __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
-               __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
-               __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
-       } else {
-               /* Save r0, r12 and restore them after usage */
-               __asm__ __volatile__("mov %0, r12":"=r"(j));
-               __asm__ __volatile__("mov %0, r0":"=r"(i));
-
-               /*
-                * GP Device ROM code API usage here
-                * r12 = AUXCR Write function and r0 value
-                */
-               __asm__ __volatile__("mov r12, #0x3");
-               __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
-               __asm__ __volatile__("bic r0, r0, #0x2");
-               /* SMI instruction to call ROM Code API */
-               __asm__ __volatile__(".word 0xE1600070");
-               __asm__ __volatile__("mov r0, %0":"=r"(i));
-               __asm__ __volatile__("mov r12, %0":"=r"(j));
-       }
-}
-
-int icache_status(void)
-{
-       return (get_cr() & CR_I) != 0;
-}
-
 static void cache_flush(void)
 {
        asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));