Merge branch 'next' of git://git.denx.de/u-boot-coldfire

[oweals/u-boot.git] / cpu / arm926ejs / cpu.c

diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c
index d1748c9c6d576397830a7ec3fd324c5e86e56969..5c902dfc133dea358d1e81a4a37e552d7603ee6b 100644 (file)
--- a/cpu/arm926ejs/cpu.c
+++ b/cpu/arm926ejs/cpu.c
@@ -4,7 +4,7 @@
  * Marius Groeger <mgroeger@sysgo.de>
  *
  * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -31,32 +31,9 @@
 
 #include <common.h>
 #include <command.h>
-#include <arm926ejs.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-static void cp_delay (void)
-{
-       volatile int i;
-
-       /* copro seems to need some delay between reading and writing */
-       for (i = 0; i < 100; i++);
-}
-
-int cpu_init (void)
-{
-       /*
-        * setup up stacks if necessary
-        */
-#ifdef CONFIG_USE_IRQ
-       IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-       FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-       return 0;
-}
+static void cache_flush(void);
 
 int cleanup_before_linux (void)
 {
@@ -67,76 +44,22 @@ int cleanup_before_linux (void)
         * we turn off caches etc ...
         */
 
-       unsigned long i;
-
        disable_interrupts ();
 
-       /* turn off I/D-cache */
-       asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-       i &= ~(CR_C | CR_I);
-       asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 
+       /* turn off I/D-cache */
+       icache_disable();
+       dcache_disable();
        /* flush I/D-cache */
-       i = 0;
-       asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
-
-       return (0);
-}
-
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-       disable_interrupts ();
-       reset_cpu (0);
-       /*NOTREACHED*/
-       return (0);
-}
-
-/* cache_bit must be either CR_I or CR_C */
-static void cache_enable(uint32_t cache_bit)
-{
-       uint32_t reg;
-
-       reg = get_cr(); /* get control reg. */
-       cp_delay();
-       set_cr(reg | cache_bit);
-}
+       cache_flush();
 
-/* cache_bit must be either CR_I or CR_C */
-static void cache_disable(uint32_t cache_bit)
-{
-       uint32_t reg;
-
-       reg = get_cr();
-       cp_delay();
-       set_cr(reg & ~cache_bit);
-}
-
-void icache_enable(void)
-{
-       cache_enable(CR_I);
-}
-
-void icache_disable(void)
-{
-       cache_disable(CR_I);
-}
-
-int icache_status(void)
-{
-       return (get_cr() & CR_I) != 0;
-}
-
-void dcache_enable(void)
-{
-       cache_enable(CR_C);
+       return 0;
 }
 
-void dcache_disable(void)
+/* flush I/D-cache */
+static void cache_flush (void)
 {
-       cache_disable(CR_C);
-}
+       unsigned long i = 0;
 
-int dcache_status(void)
-{
-       return (get_cr() & CR_C) != 0;
+       asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
 }