* Code cleanup

[oweals/u-boot.git] / cpu / arm920t / start.S

diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index 0e372d0e4ceb5ebcef10ddeff9355eaf9b16cd69..78c470d7b69fd5e07b832674f916ad30e1c77d3f 100644 (file)
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -118,20 +118,17 @@ reset:
 
 /* turn off the watchdog */
 #if defined(CONFIG_S3C2400)
-#define pWTCON         0x15300000
-/* Interupt-Controller base addresses */
-#define INTMSK         0x14400008
-/* clock divisor register */
-#define CLKDIVN                0x14800014
+# define pWTCON                0x15300000
+# define INTMSK                0x14400008      /* Interupt-Controller base addresses */
+# define CLKDIVN       0x14800014      /* clock divisor register */
 #elif defined(CONFIG_S3C2410)
-#define pWTCON         0x53000000
-/* Interupt-Controller base addresses */
-#define INTMSK         0x4A000008
-#define INTSUBMSK      0x4A00001C
-/* clock divisor register */
-#define CLKDIVN                0x4C000014
+# define pWTCON                0x53000000
+# define INTMSK                0x4A000008      /* Interupt-Controller base addresses */
+# define INTSUBMSK     0x4A00001C
+# define CLKDIVN       0x4C000014      /* clock divisor register */
 #endif
 
+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
        ldr     r0, =pWTCON
        mov     r1, #0x0
        str     r1, [r0]
@@ -142,17 +139,18 @@ reset:
        mov     r1, #0xffffffff
        ldr     r0, =INTMSK
        str     r1, [r0]
-#if defined(CONFIG_S3C2410)
+# if defined(CONFIG_S3C2410)
        ldr     r1, =0x3ff
        ldr     r0, =INTSUBMSK
        str     r1, [r0]
-#endif
+# endif
 
        /* FCLK:HCLK:PCLK = 1:2:4 */
        /* default FCLK is 120 MHz ! */
        ldr     r0, =CLKDIVN
        mov     r1, #3
        str     r1, [r0]
+#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
 
        /*
         * we do sys-critical inits only at reboot,