Merge branch 'next' of git://git.denx.de/u-boot-avr32

[oweals/u-boot.git] / cpu / arm920t / s3c24x0 / interrupts.c

diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c
index 868621fa5e91ddbacef46bb24ac4b2b26f7146d4..7ad9fcbd5bad0a9096a0ead97a11bfb05ea1e4b1 100644 (file)
--- a/cpu/arm920t/s3c24x0/interrupts.c
+++ b/cpu/arm920t/s3c24x0/interrupts.c
@@ -176,7 +176,9 @@ ulong get_tbclk (void)
 
 #if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
        tbclk = timer_load_val * 100;
-#elif defined(CONFIG_SMDK2410) || defined(CONFIG_VCMA9)
+#elif defined(CONFIG_SBC2410X) || \
+      defined(CONFIG_SMDK2410) || \
+      defined(CONFIG_VCMA9)
        tbclk = CFG_HZ;
 #else
 #      error "tbclk not configured"
@@ -185,4 +187,42 @@ ulong get_tbclk (void)
        return tbclk;
 }
 
+/*
+ * reset the cpu by setting up the watchdog timer and let him time out
+ */
+void reset_cpu (ulong ignored)
+{
+       volatile S3C24X0_WATCHDOG * watchdog;
+
+#ifdef CONFIG_TRAB
+       extern void disable_vfd (void);
+
+       disable_vfd();
+#endif
+
+       watchdog = S3C24X0_GetBase_WATCHDOG();
+
+       /* Disable watchdog */
+       watchdog->WTCON = 0x0000;
+
+       /* Initialize watchdog timer count register */
+       watchdog->WTCNT = 0x0001;
+
+       /* Enable watchdog timer; assert reset at timer timeout */
+       watchdog->WTCON = 0x0021;
+
+       while(1);       /* loop forever and wait for reset to happen */
+
+       /*NOTREACHED*/
+}
+
+#ifdef CONFIG_USE_IRQ
+void s3c2410_irq(void)
+{
+       S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT();
+       u_int32_t intpnd = irq->INTPND;
+
+}
+#endif /* USE_IRQ */
+
 #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */