i386: Replace [read, write]_mmcr_[byte, word, long] with memory mapped structure

[oweals/u-boot.git] / cpu / arm1136 / cpu.c

diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c
index 0abe307bb22c747da3da1cebaa3b50f3aa7b8830..ade7f4680077bd2f72892154abe7c7f85c2f5a93 100644 (file)
--- a/cpu/arm1136/cpu.c
+++ b/cpu/arm1136/cpu.c
@@ -6,7 +6,7 @@
  * Marius Groeger <mgroeger@sysgo.de>
  *
  * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -35,29 +35,7 @@
 #include <command.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-static void cp_delay (void)
-{
-       volatile int i;
-
-       /* Many OMAP regs need at least 2 nops  */
-       for (i = 0; i < 100; i++);
-}
-
-int cpu_init (void)
-{
-       /*
-        * setup up stacks if necessary
-        */
-#ifdef CONFIG_USE_IRQ
-       IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-       FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-       return 0;
-}
+static void cache_flush(void);
 
 int cleanup_before_linux (void)
 {
@@ -68,8 +46,6 @@ int cleanup_before_linux (void)
         * we turn off caches etc ...
         */
 
-       unsigned long i;
-
        disable_interrupts ();
 
 #ifdef CONFIG_LCD
@@ -83,44 +59,18 @@ int cleanup_before_linux (void)
 #endif
 
        /* turn off I/D-cache */
-       asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-       i &= ~(CR_C | CR_I);
-       asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-
+       icache_disable();
+       dcache_disable();
        /* flush I/D-cache */
-       i = 0;
-       asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  /* invalidate both caches and flush btb */
-       asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
-       return(0);
-}
-
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-       disable_interrupts ();
-       reset_cpu (0);
-       /*NOTREACHED*/
-       return(0);
-}
-
-void icache_enable (void)
-{
-       ulong reg;
+       cache_flush();
 
-       reg = get_cr ();        /* get control reg. */
-       cp_delay ();
-       set_cr (reg | CR_I);
+       return 0;
 }
 
-void icache_disable (void)
+static void cache_flush(void)
 {
-       ulong reg;
-
-       reg = get_cr ();
-       cp_delay ();
-       set_cr (reg & ~CR_I);
-}
+       unsigned long i = 0;
 
-int icache_status (void)
-{
-       return(get_cr () & CR_I) != 0;
+       asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  /* invalidate both caches and flush btb */
+       asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
 }