rockchip: Kconfig: enable SPL support for rk3328
[oweals/u-boot.git] / configs / kmcoge5ne_defconfig
index a358e28886c3233c3578453a1f74d000d590a660..faeb0c7175af3211b9aecf59c5086d20c272dcac 100644 (file)
@@ -1,5 +1,6 @@
 CONFIG_PPC=y
 CONFIG_SYS_TEXT_BASE=0xF0000000
+CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8
 CONFIG_SYS_CLK_FREQ=66000000
 CONFIG_MPC83xx=y
 CONFIG_HIGH_BATS=y
@@ -92,6 +93,65 @@ CONFIG_BAT7_DCACHE_INHIBITED=y
 CONFIG_BAT7_DCACHE_GUARDED=y
 CONFIG_BAT7_USER_MODE_VALID=y
 CONFIG_BAT7_SUPERVISOR_MODE_VALID=y
+CONFIG_LBLAW0=y
+CONFIG_LBLAW0_BASE=0xF0000000
+CONFIG_LBLAW0_NAME="FLASH"
+CONFIG_LBLAW0_LENGTH_256_MBYTES=y
+CONFIG_LBLAW1=y
+CONFIG_LBLAW1_BASE=0xE8000000
+CONFIG_LBLAW1_NAME="KMBEC_FPGA"
+CONFIG_LBLAW1_LENGTH_128_MBYTES=y
+CONFIG_LBLAW3=y
+CONFIG_LBLAW3_BASE=0xA0000000
+CONFIG_LBLAW3_NAME="PAXE"
+CONFIG_LBLAW3_LENGTH_512_MBYTES=y
+CONFIG_ELBC_BR0_OR0=y
+CONFIG_BR0_OR0_NAME="FLASH"
+CONFIG_BR0_OR0_BASE=0xF0000000
+CONFIG_BR0_PORTSIZE_16BIT=y
+CONFIG_OR0_AM_256_MBYTES=y
+CONFIG_OR0_SCY_5=y
+CONFIG_OR0_CSNT_EARLIER=y
+CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR0_TRLX_RELAXED=y
+CONFIG_OR0_EAD_EXTRA=y
+CONFIG_ELBC_BR1_OR1=y
+CONFIG_BR1_OR1_NAME="KMBEC_FPGA"
+CONFIG_BR1_OR1_BASE=0xE8000000
+CONFIG_OR1_AM_64_MBYTES=y
+CONFIG_OR1_SCY_2=y
+CONFIG_OR1_CSNT_EARLIER=y
+CONFIG_OR1_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR1_TRLX_RELAXED=y
+CONFIG_OR1_EAD_EXTRA=y
+CONFIG_ELBC_BR3_OR3=y
+CONFIG_BR3_OR3_NAME="PAXE"
+CONFIG_BR3_OR3_BASE=0xA0000000
+CONFIG_OR3_AM_256_MBYTES=y
+CONFIG_OR3_SCY_2=y
+CONFIG_OR3_CSNT_EARLIER=y
+CONFIG_OR3_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR3_TRLX_RELAXED=y
+CONFIG_OR3_EAD_EXTRA=y
+CONFIG_ELBC_BR4_OR4=y
+CONFIG_BR4_OR4_NAME="BFTIC3"
+CONFIG_BR4_OR4_BASE=0xB0000000
+CONFIG_OR4_AM_256_MBYTES=y
+CONFIG_OR4_SCY_2=y
+CONFIG_OR4_CSNT_EARLIER=y
+CONFIG_OR4_ACS_HALF_CYCLE_EARLIER=y
+CONFIG_OR4_TRLX_RELAXED=y
+CONFIG_OR4_EAD_EXTRA=y
+CONFIG_HID0_FINAL_EMCP=y
+CONFIG_HID0_FINAL_ICE=y
+CONFIG_HID2_HBE=y
+CONFIG_ACR_PIPE_DEP_4=y
+CONFIG_ACR_RPTCNT_4=y
+CONFIG_ACR_APARK_MASTER=y
+CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
+CONFIG_LCRR_DBYP_PLL_BYPASSED=y
+CONFIG_LCRR_EADC_2=y
+CONFIG_LCRR_CLKDIV_4=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_MISC_INIT_R=y
@@ -119,7 +179,6 @@ CONFIG_CMD_UBI=y
 # CONFIG_CMD_UBIFS is not set
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
-CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
@@ -128,6 +187,7 @@ CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 # CONFIG_PCI is not set
+CONFIG_QE=y
 CONFIG_SYS_NS16550=y
 CONFIG_BCH=y
 CONFIG_OF_LIBFDT=y