nand: Remove unused ppc4xx NAND driver and references

[oweals/u-boot.git] / board / xilinx / zynq / board.c

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 4bb140e29ec0cb5f72c512db0dc8d74e7c3d2e3a..fb8eab07d76820dbc5fcc77756205b919d538a7e 100644 (file)
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -1,53 +1,82 @@
 /*
  * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ * (C) Copyright 2013 - 2018 Xilinx, Inc.
  *
- * SPDX-License-Identifier:    GPL-2.0+ 
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
-#include <netdev.h>
+#include <fdtdec.h>
+#include <fpga.h>
+#include <mmc.h>
 #include <zynqpl.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/ps7_init_gpl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_FPGA
-Xilinx_desc fpga;
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static xilinx_desc fpga;
 
 /* It can be done differently */
-Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
-Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
-Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
-Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
+static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
+static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
+static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
+static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
+static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
+static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
+static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
 #endif
 
 int board_init(void)
 {
-#ifdef CONFIG_FPGA
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
        u32 idcode;
 
        idcode = zynq_slcr_get_idcode();
 
        switch (idcode) {
+       case XILINX_ZYNQ_7007S:
+               fpga = fpga007s;
+               break;
        case XILINX_ZYNQ_7010:
                fpga = fpga010;
                break;
+       case XILINX_ZYNQ_7012S:
+               fpga = fpga012s;
+               break;
+       case XILINX_ZYNQ_7014S:
+               fpga = fpga014s;
+               break;
+       case XILINX_ZYNQ_7015:
+               fpga = fpga015;
+               break;
        case XILINX_ZYNQ_7020:
                fpga = fpga020;
                break;
        case XILINX_ZYNQ_7030:
                fpga = fpga030;
                break;
+       case XILINX_ZYNQ_7035:
+               fpga = fpga035;
+               break;
        case XILINX_ZYNQ_7045:
                fpga = fpga045;
                break;
+       case XILINX_ZYNQ_7100:
+               fpga = fpga100;
+               break;
        }
 #endif
 
-       icache_enable();
-
-#ifdef CONFIG_FPGA
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
        fpga_init();
        fpga_add(fpga_xilinx, &fpga);
 #endif
@@ -55,46 +84,83 @@ int board_init(void)
        return 0;
 }
 
+int board_late_init(void)
+{
+       switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+       case ZYNQ_BM_QSPI:
+               env_set("modeboot", "qspiboot");
+               break;
+       case ZYNQ_BM_NAND:
+               env_set("modeboot", "nandboot");
+               break;
+       case ZYNQ_BM_NOR:
+               env_set("modeboot", "norboot");
+               break;
+       case ZYNQ_BM_SD:
+               env_set("modeboot", "sdboot");
+               break;
+       case ZYNQ_BM_JTAG:
+               env_set("modeboot", "jtagboot");
+               break;
+       default:
+               env_set("modeboot", "");
+               break;
+       }
 
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
+       return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
 {
-       u32 ret = 0;
-
-#if defined(CONFIG_ZYNQ_GEM)
-# if defined(CONFIG_ZYNQ_GEM0)
-       ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
-                                               CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
-# endif
-# if defined(CONFIG_ZYNQ_GEM1)
-       ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
-                                               CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
-# endif
-#endif
-       return ret;
+       u32 version = zynq_get_silicon_version();
+
+       version <<= 1;
+       if (version > (PCW_SILICON_VERSION_3 << 1))
+               version += 1;
+
+       puts("Board: Xilinx Zynq\n");
+       printf("Silicon: v%d.%d\n", version >> 1, version & 1);
+
+       return 0;
 }
 #endif
 
-#ifdef CONFIG_CMD_MMC
-int board_mmc_init(bd_t *bd)
+int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
 {
-       int ret = 0;
-
-#if defined(CONFIG_ZYNQ_SDHCI)
-# if defined(CONFIG_ZYNQ_SDHCI0)
-       ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
-# endif
-# if defined(CONFIG_ZYNQ_SDHCI1)
-       ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
-# endif
+#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
+    defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
+       if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
+                       CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
+                       ethaddr, 6))
+               printf("I2C EEPROM MAC address read failed\n");
 #endif
-       return ret;
+
+       return 0;
+}
+
+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
+int dram_init_banksize(void)
+{
+       return fdtdec_setup_memory_banksize();
 }
-#endif
 
+int dram_init(void)
+{
+       if (fdtdec_setup_memory_size() != 0)
+               return -EINVAL;
+
+       zynq_ddrc_init();
+
+       return 0;
+}
+#else
 int dram_init(void)
 {
        gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 
+       zynq_ddrc_init();
+
        return 0;
 }
+#endif