#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
-#define XPAR_INTC_0_BASEADDR 0x81800000
-#define XPAR_UARTLITE_0_BASEADDR 0x84000000
-#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
+#define XPAR_INTC_0_BASEADDR 0x87000000
+#define XPAR_FLASH_MEM0_BASEADDR 0xF0000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
-#define XPAR_UARTLITE_0_BAUDRATE 9600
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
+#define XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR 0x80
+#define XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR 0x98
+#define XPAR_LLTEMAC_0_BASEADDR 0x83000000
+#define XPAR_LLTEMAC_1_BASEADDR 0x83000040
#endif