powerpc: P1023: Remove macro CONFIG_P1023

[oweals/u-boot.git] / board / xilinx / ppc440-generic / xparameters.h

diff --git a/board/xilinx/ppc440-generic/xparameters.h b/board/xilinx/ppc440-generic/xparameters.h
index 1992fff22047365b222a6f3974c1c218939cc532..b45a6a1d7668176e2c595992740d325618dd43e2 100644 (file)
--- a/board/xilinx/ppc440-generic/xparameters.h
+++ b/board/xilinx/ppc440-generic/xparameters.h
@@ -1,21 +1,10 @@
 /*
  * (C) Copyright 2008
- * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
  * This work has been supported by: QTechnology  http://qtec.com/
  * based on xparameters-ml507.h by Xilinx
  *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier:    GPL-2.0+
 */
 
 #ifndef XPARAMETER_H
@@ -23,12 +12,15 @@
 
 #define XPAR_DDR2_SDRAM_MEM_BASEADDR   0x00000000
 #define XPAR_IIC_EEPROM_BASEADDR       0x81600000
-#define XPAR_INTC_0_BASEADDR           0x81800000
-#define XPAR_UARTLITE_0_BASEADDR       0x84000000
-#define XPAR_FLASH_MEM0_BASEADDR       0xFE000000
+#define XPAR_INTC_0_BASEADDR           0x87000000
+#define XPAR_FLASH_MEM0_BASEADDR       0xF0000000
 #define XPAR_PLB_CLOCK_FREQ_HZ         100000000
 #define XPAR_CORE_CLOCK_FREQ_HZ                400000000
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS  13
-#define XPAR_UARTLITE_0_BAUDRATE       9600
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS  32
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
+#define XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR 0x80
+#define XPAR_LLTEMAC_1_LLINK_CONNECTED_BASEADDR 0x98
+#define XPAR_LLTEMAC_0_BASEADDR                0x83000000
+#define XPAR_LLTEMAC_1_BASEADDR                0x83000040
 
 #endif