Merge branch 'master' of git://www.denx.de/git/u-boot-nand-flash

[oweals/u-boot.git] / board / xilinx / ml401 / xparameters.h

diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h
index 18d24f9c1d1ed07d195531dc133f800db6d023f4..d805061c0d01b17d20d91f57db931685f9ef6bc8 100644 (file)
--- a/board/xilinx/ml401/xparameters.h
+++ b/board/xilinx/ml401/xparameters.h
@@ -21,47 +21,49 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  *
- *
  * CAUTION: This file is automatically generated by libgen.
- * Version: Xilinx EDK 6.3 EDK_Gmm.12.3
+ * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
  */
 
 /* System Clock Frequency */
-#define XILINX_CLOCK_FREQ      66666667
+#define XILINX_CLOCK_FREQ      100000000
+
+/* Microblaze is microblaze_0 */
+#define XILINX_USE_MSR_INSTR   1
+#define XILINX_FSL_NUMBER      3
 
-/* Interrupt controller is intc_0 */
-#define XILINX_INTC_BASEADDR   0xd1000fc0
-#define XILINX_INTC_NUM_INTR_INPUTS    12
+/* Interrupt controller is opb_intc_0 */
+#define XILINX_INTC_BASEADDR   0x41200000
+#define XILINX_INTC_NUM_INTR_INPUTS    6
 
-/* Timer pheriphery is opb_timer_0 */
-#define XILINX_TIMER_BASEADDR  0xa2000000
+/* Timer pheriphery is opb_timer_1 */
+#define XILINX_TIMER_BASEADDR  0x41c00000
 #define XILINX_TIMER_IRQ       0
 
-/* Uart pheriphery is console_uart */
-#define XILINX_UART_BASEADDR   0xa0000000
-#define XILINX_UART_BAUDRATE   115200
+/* Uart pheriphery is RS232_Uart */
+#define XILINX_UARTLITE_BASEADDR       0x40600000
+#define XILINX_UARTLITE_BAUDRATE       115200
+
+/* IIC pheriphery is IIC_EEPROM */
+#define XILINX_IIC_0_BASEADDR  0x40800000
+#define XILINX_IIC_0_FREQ      100000
+#define XILINX_IIC_0_BIT       0
 
-/* GPIO is opb_gpio_0*/
-#define XILINX_GPIO_BASEADDR   0x90000000
+/* GPIO is LEDs_4Bit*/
+#define XILINX_GPIO_BASEADDR   0x40000000
 
-/* Flash Memory is opb_emc_0 */
-#define XILINX_FLASH_START     0x28000000
+/* Flash Memory is FLASH_2Mx32 */
+#define XILINX_FLASH_START     0x2c000000
 #define XILINX_FLASH_SIZE      0x00800000
 
-/* Main Memory is plb_ddr_0 */
-#define XILINX_RAM_START       0x10000000
-#define XILINX_RAM_SIZE        0x10000000
+/* Main Memory is DDR_SDRAM_64Mx32 */
+#define XILINX_RAM_START       0x28000000
+#define XILINX_RAM_SIZE        0x04000000
 
-/* Sysace Controller is opb_sysace_0 */
-#define XILINX_SYSACE_BASEADDR 0xCF000000
-#define XILINX_SYSACE_HIGHADDR 0xCF0001FF
+/* Sysace Controller is SysACE_CompactFlash */
+#define XILINX_SYSACE_BASEADDR 0x41800000
+#define XILINX_SYSACE_HIGHADDR 0x4180ffff
 #define XILINX_SYSACE_MEM_WIDTH        16
 
-/* Ethernet controller is opb_ethernet_0 */
-#define XPAR_XEMAC_NUM_INSTANCES       1
-#define XPAR_OPB_ETHERNET_0_DEVICE_ID  0
-#define XPAR_OPB_ETHERNET_0_BASEADDR   0x60000000
-#define XPAR_OPB_ETHERNET_0_HIGHADDR   0x60003FFF
-#define XPAR_OPB_ETHERNET_0_DMA_PRESENT        1
-#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST    1
-#define XPAR_OPB_ETHERNET_0_MII_EXIST  1
+/* Ethernet controller is Ethernet_MAC */
+#define XILINX_EMACLITE_BASEADDR       0x40C00000