* and
* Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
/*
* Description:
* Routine to exercise memory for the bringing up of our boards.
*/
#include <config.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
* Switch to .data section.
*/
.section ".data"
-err_str: .asciz "*** POST ERROR = "
+err_str: .asciz "*** POST ERROR = "
warn_str: .asciz "*** POST WARNING = "
end_str: .asciz "\r\n"
stw r0, +16(r1) /* Save link register */
stw r4, +8(r1) /* save R4 */
- WATCHDOG_RESET /* Reset the watchdog */
+ WATCHDOG_RESET /* Reset the watchdog */
addi r3, 0, ERR_FF /* first test value is ffff */
addi r4, r3, 0 /* save copy of pattern */
addi r31, r3, 0 /* save original size */
/* now kick the dog and test the mem */
- WATCHDOG_RESET /* Reset the watchdog */
+ WATCHDOG_RESET /* Reset the watchdog */
bl Data_Buster /* test crossed/shorted data lines */
addi r3, r30, 0 /* get log2(memsize) */
addi r4, r31, 0 /* get memsize */
addi r28, r28, 4 /* Increment to next word */
andi. r27, r28, 0xffff /* check for 2^16 loops */
bne clr_skip /* if not there, then skip */
- WATCHDOG_RESET /* kick the dog every now and then */
+ WATCHDOG_RESET /* kick the dog every now and then */
clr_skip:
bdnz clr_loop /* Round and round... */
* thus the sequence 0,1,2,4,8,..,2^(n-1)
* setting the bit is done with the following shift functions.
*/
- WATCHDOG_RESET /* Reset the watchdog */
+ WATCHDOG_RESET /* Reset the watchdog */
addi r31, 0, 1 /* r31 = 1 */
slw r28, r31, r30 /* set bit coresponding to loop cnt */
addi r31, 0, 0x00ff /* r31 = one byte of set bits */
stb r31,0(r28) /* save ff in referance address */
- /* ghost (inner) loop, now check all posible ghosted addresses */
+ /* ghost (inner) loop, now check all posible ghosted addresses */
addi r29, 0, 0 /* start ghosted loop counter at 0 */
inside:
/*
bne Casper /* we found a ghost! */
/* now close ghost ( inner ) loop */
- addi r29, r29, 1 /* increment inner loop counter */
- cmpw r29, r26 /* check for last inner loop */
+ addi r29, r29, 1 /* increment inner loop counter */
+ cmpw r29, r26 /* check for last inner loop */
blt inside /* do more inner loops */
/* now close referance ( outer ) loop */
- addi r31, 0, 0 /* r31 = zero */
+ addi r31, 0, 0 /* r31 = zero */
stb r31, 0(28) /* zero out the altered address loc. */
/*
* Increment and check for end, count is zero based.
* With the ble, this gives us one more loops than
* address bits for sequence 0,1,2,4,8,...2^(n-1)
*/
- addi r30, r30, 1 /* increment outer loop counter */
- cmpw r30, r26 /* check for last inner loop */
+ addi r30, r30, 1 /* increment outer loop counter */
+ cmpw r30, r26 /* check for last inner loop */
ble outside /* do more outer loops */
/* were done, lets go home */
addi r3, 0, ERR_ADDF /* get indexed error message */
bl log_err /* log error led error code */
gb_done: /* pack your bags, and go home */
- lmw r25, 8(r1) /* restore r25 - r31 from stack */
- lwz r0, +40(r1) /* Get saved link register */
- addi r1, r1, +36 /* Remove frame from stack */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
+ lmw r25, 8(r1) /* restore r25 - r31 from stack */
+ lwz r0, +40(r1) /* Get saved link register */
+ addi r1, r1, +36 /* Remove frame from stack */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
/****************************************************
******** SDRAM data fill tests **********
blr /* Return to calling function */
-
/****************************************************
******** fill test ********
***************************************************/
/* r4 = Value to write */
/* r3 = Error code */
fill_test:
- mflr r0 /* Get link register */
- stwu r1, -32(r1) /* Save back chain and move SP */
- stw r0, +36(r1) /* Save link register */
- stmw r27, 8(r1) /* save r27 - r31 on stack */
- /* r31 - scratch register */
- /* r30 - memory address */
+ mflr r0 /* Get link register */
+ stwu r1, -32(r1) /* Save back chain and move SP */
+ stw r0, +36(r1) /* Save link register */
+ stmw r27, 8(r1) /* save r27 - r31 on stack */
+ /* r31 - scratch register */
+ /* r30 - memory address */
mr r27, r3
mr r28, r4
mr r29, r5
- WATCHDOG_RESET /* Reset the watchdog */
+ WATCHDOG_RESET /* Reset the watchdog */
/* first fill memory with Value */
srawi r31, r29, 2 /* convert bytes to longs */
addi r30, r30, 4 /* Increment to next word */
andi. r31, r30, 0xffff /* check for 2^16 loops */
bne ft_0a /* if not there, then skip */
- WATCHDOG_RESET /* kick the dog every now and then */
+ WATCHDOG_RESET /* kick the dog every now and then */
ft_0a: bdnz ft_0 /* Round and round... */
- WATCHDOG_RESET /* Reset the watchdog */
+ WATCHDOG_RESET /* Reset the watchdog */
/* Now confirm Value is in memory */
srawi r31, r29, 2 /* convert bytes to longs */
mtctr r31 /* setup counter */
addi r30, 0, 0 /* Make r30 = addr 0 */
ft_1: lwz r31, 0(r30) /* get value from memory */
- xor. r31, r31, r28 /* Writen = Read ? */
- bne ft_err /* If bad, than halt */
+ xor. r31, r31, r28 /* Writen = Read ? */
+ bne ft_err /* If bad, than halt */
addi r30, r30, 4 /* Increment to next word */
andi. r31, r30, 0xffff /* check for 2^16 loops*/
bne ft_1a /* if not there, then skip */
WATCHDOG_RESET /* kick the dog every now and then */
ft_1a: bdnz ft_1 /* Round and round... */
- WATCHDOG_RESET /* Reset the watchdog */
+ WATCHDOG_RESET /* Reset the watchdog */
b fill_done /* restore and return */
bl log_err /* output led err code, halt CPU */
fill_done:
- lmw r27, 8(r1) /* restore r27 - r31 from stack */
- lwz r0, +36(r1) /* Get saved link register */
- addi r1, r1, +32 /* Remove frame from stack */
- mtlr r0 /* Restore link register */
- blr /* Return to calling function */
+ lmw r27, 8(r1) /* restore r27 - r31 from stack */
+ lwz r0, +36(r1) /* Get saved link register */
+ addi r1, r1, +32 /* Remove frame from stack */
+ mtlr r0 /* Restore link register */
+ blr /* Return to calling function */
/****************************************************
mtctr r3
log_2:
WATCHDOG_RESET /* this keeps dog from barking, */
- /* and takes time */
+ /* and takes time */
bdnz log_2 /* loop till time expires */
/* restore stack and return */
stwu r1, -8(r1) /* Save back chain and move SP */
stw r0, +12(r1) /* Save link register */
- addis r3, 0, 0xef60
- ori r3, r3, 0x0303 /* r3 = UART0_LCR */
- addi r4, 0, 0x83 /* n81 format, divisor regs enabled */
- stb r4, 0(r3)
+ addis r3, 0, 0xef60
+ ori r3, r3, 0x0303 /* r3 = UART0_LCR */
+ addi r4, 0, 0x83 /* n81 format, divisor regs enabled */
+ stb r4, 0(r3)
/* set baud rate to use internal clock,
baud = (200e6/16)/31/42 = 9600 */
- addis r3, 0, 0xef60 /* Address of baud divisor reg */
- ori r3, r3, 0x0300 /* UART0_DLM */
- addi r4, 0, +42 /* uart baud divisor LSB = 93 */
- stb r4, 0(r3) /* baud = (200 /16)/14/93 */
+ addis r3, 0, 0xef60 /* Address of baud divisor reg */
+ ori r3, r3, 0x0300 /* UART0_DLM */
+ addi r4, 0, +42 /* uart baud divisor LSB = 93 */
+ stb r4, 0(r3) /* baud = (200 /16)/14/93 */
- addi r3, r3, 0x0001 /* uart baud divisor addr */
- addi r4, 0, 0
- stb r4, 0(r3) /* Divisor Latch MSB = 0 */
+ addi r3, r3, 0x0001 /* uart baud divisor addr */
+ addi r4, 0, 0
+ stb r4, 0(r3) /* Divisor Latch MSB = 0 */
- addis r3, 0, 0xef60
- ori r3, r3, 0x0303 /* r3 = UART0_LCR */
- addi r4, 0, 0x03 /* n81 format, tx/rx regs enabled */
- stb r4, 0(r3)
+ addis r3, 0, 0xef60
+ ori r3, r3, 0x0303 /* r3 = UART0_LCR */
+ addi r4, 0, 0x03 /* n81 format, tx/rx regs enabled */
+ stb r4, 0(r3)
/* output a few line feeds */
addi r3, 0, '\n' /* load line feed */
- bl post_putc /* output the char */
+ bl post_putc /* output the char */
addi r3, 0, '\n' /* load line feed */
- bl post_putc /* output the char */
+ bl post_putc /* output the char */
- /* restore stack and return */
+ /* restore stack and return */
lwz r0, +12(r1) /* Get saved link register */
mtlr r0 /* Restore link register */
addi r1, r1, +8 /* Remove frame from stack */
stw r0, +24(r1) /* Save link register */
stmw r29, 8(r1) /* save r29 - r31 on stack
r31 - uart base address
- r30 - delay counter
+ r30 - delay counter
r29 - scratch reg */
addis r31, 0, 0xef60 /* Point to uart base */
ori r31, r31, 0x0300
- addis r30, 0, 152 /* Load about 10,000,000 ticks. */
+ addis r30, 0, 152 /* Load about 10,000,000 ticks. */
pputc_lp:
- lbz r29, 5(r31) /* Read Line Status Register */
+ lbz r29, 5(r31) /* Read Line Status Register */
andi. r29, r29, 0x20 /* Check THRE status */
bne thre_set /* Branch if FIFO empty */
addic. r30, r30, -1 /* Decrement and check if empty. */
bne pputc_lp /* Try, try again */
addi r3, 0, -1 /* Load error code for timeout */
- b pputc_done /* Bail out with error code set */
+ b pputc_done /* Bail out with error code set */
thre_set:
stb r3, 0(r31) /* Store character to UART */
addi r3, 0, 0 /* clear error code */
stw r0, +16(r1) /* Save link register */
stw r31, 8(r1) /* save r31 - char pointer */
- addi r31, r3, 0 /* move pointer to R31 */
+ addi r31, r3, 0 /* move pointer to R31 */
pputs_nxt:
lbz r3, 0(r31) /* Get next character */
addic. r3, r3, 0 /* Check for zero */
bl post_putc /* output the char */
addic. r3, r3, 0 /* check for error */
bne pputs_err
- addi r31, r31, 1 /* point to next char */
- b pputs_nxt /* loop till term */
+ addi r31, r31, 1 /* point to next char */
+ b pputs_nxt /* loop till term */
pputs_err:
- addi r3, 0, -1 /* set error code */
+ addi r3, 0, -1 /* set error code */
b pputs_end /* were outa here */
pputs_term:
- addi r3, 0, 1 /* set success code */
- /* restore stack and return */
+ addi r3, 0, 1 /* set success code */
+ /* restore stack and return */
pputs_end:
lwz r31, 8(r1) /* restore r27 - r31 from stack */
lwz r0, +16(r1) /* Get saved link register */
blr /* Return to calling function */
-
/********************************************************************
***** disp_hex
***** Routine to display a hex value from a register.
stmw r30, 8(r1) /* save r30 - r31 on stack */
/* r31 output char */
/* r30 uart base address */
- addi r30, 0, 8 /* Go through 8 nibbles. */
- addi r31, r3, 0
+ addi r30, 0, 8 /* Go through 8 nibbles. */
+ addi r31, r3, 0
pputh_nxt:
rlwinm r31, r31, 4, 0, 31 /* Rotate next nibble into position */
- andi. r3, r31, 0x0f /* Get nibble. */
- addi r3, r3, 0x30 /* Add zero's ASCII code. */
+ andi. r3, r31, 0x0f /* Get nibble. */
+ addi r3, r3, 0x30 /* Add zero's ASCII code. */
cmpwi r3, 0x03a
blt pputh_out
- addi r3, r3, 0x07 /* 0x27 for lower case. */
+ addi r3, r3, 0x07 /* 0x27 for lower case. */
pputh_out:
- cmpw r30, r4
+ cmpw r30, r4
bgt pputh_skip
bl post_putc
- addic. r3, r3, 0 /* check for error */
+ addic. r3, r3, 0 /* check for error */
bne pputh_err
pputh_skip:
addic. r30, r30, -1
xor r3, r3, r3 /* Clear error code */
b pputh_done
pputh_err:
- addi r3, 0, -1 /* set error code */
+ addi r3, 0, -1 /* set error code */
pputh_done:
- /* restore stack and return */
+ /* restore stack and return */
lmw r30, 8(r1) /* restore r30 - r31 from stack */
lwz r0, +20(r1) /* Get saved link register */
addi r1, r1, +16 /* Remove frame from stack */
mtlr r0 /* Restore link register */
blr /* Return to calling function */
-