Merge with /home/wd/git/u-boot/master

[oweals/u-boot.git] / board / tqm8xx / tqm8xx.c

diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c
index 18201f67db4a1573539c97325c6838add226d817..017bdf9442a8871ebfa737ff0faa9445c33c5e74 100644 (file)
--- a/board/tqm8xx/tqm8xx.c
+++ b/board/tqm8xx/tqm8xx.c
@@ -27,6 +27,9 @@
 
 #include <common.h>
 #include <mpc8xx.h>
+#ifdef CONFIG_PS2MULT
+#include <ps2mult.h>
+#endif
 
 /* ------------------------------------------------------------------------- */
 
@@ -103,7 +106,7 @@ int checkboard (void)
 {
        DECLARE_GLOBAL_DATA_PTR;
 
-       unsigned char *s = getenv ("serial#");
+       char *s = getenv ("serial#");
 
        puts ("Board: ");
 
@@ -136,7 +139,7 @@ long int initdram (int board_type)
 {
        volatile immap_t *immap = (immap_t *) CFG_IMMR;
        volatile memctl8xx_t *memctl = &immap->im_memctl;
-       long int size8, size9;
+       long int size8, size9, size10;
        long int size_b0 = 0;
        long int size_b1 = 0;
 
@@ -212,7 +215,7 @@ long int initdram (int board_type)
         *
         * try 8 column mode
         */
-       size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
+       size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM,
                                           SDRAM_MAX_SIZE);
        debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
 
@@ -221,13 +224,30 @@ long int initdram (int board_type)
        /*
         * try 9 column mode
         */
-       size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
+       size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM,
                                           SDRAM_MAX_SIZE);
        debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
 
-       if (size8 < size9) {            /* leave configuration at 9 columns */
+       udelay(1000);
+
+#if defined(CFG_MAMR_10COL)
+       /*
+        * try 10 column mode
+        */
+       size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE2_PRELIM,
+                                            SDRAM_MAX_SIZE);
+       debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
+#else
+       size10 = 0;
+#endif /* CFG_MAMR_10COL */
+
+       if ((size8 < size10) && (size9 < size10)) {
+               size_b0 = size10;
+       } else if ((size8 < size9) && (size10 < size9)) {
                size_b0 = size9;
-       } else {                                        /* back to 8 columns            */
+               memctl->memc_mamr = CFG_MAMR_9COL;
+               udelay (500);
+       } else {
                size_b0 = size8;
                memctl->memc_mamr = CFG_MAMR_8COL;
                udelay (500);
@@ -243,7 +263,7 @@ long int initdram (int board_type)
                 * [9 column SDRAM may also be used in 8 column mode,
                 *  but then only half the real size will be used.]
                 */
-               size_b1 = dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
+               size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
                                     SDRAM_MAX_SIZE);
                debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
        } else {
@@ -269,18 +289,15 @@ long int initdram (int board_type)
        if (size_b1 > size_b0) {        /* SDRAM Bank 1 is bigger - map first   */
 
                memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-               memctl->memc_br3 =
-                               (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+               memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
                if (size_b0 > 0) {
                        /*
                         * Position Bank 0 immediately above Bank 1
                         */
-                       memctl->memc_or2 =
-                                       ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-                       memctl->memc_br2 =
-                                       ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
-                                       + size_b1;
+                       memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+                       memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+                                          + size_b1;
                } else {
                        unsigned long reg;
 
@@ -405,3 +422,80 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
 }
 
 /* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_PS2MULT
+
+#ifdef CONFIG_HMI10
+#define BASE_BAUD ( 1843200 / 16 )
+struct serial_state rs_table[] = {
+       { BASE_BAUD, 4,  (void*)0xec140000 },
+       { BASE_BAUD, 2,  (void*)0xec150000 },
+       { BASE_BAUD, 6,  (void*)0xec160000 },
+       { BASE_BAUD, 10, (void*)0xec170000 },
+};
+
+#ifdef CONFIG_BOARD_EARLY_INIT_R
+int board_early_init_r (void)
+{
+       ps2mult_early_init();
+       return (0);
+}
+#endif
+#endif /* CONFIG_HMI10 */
+
+#endif /* CONFIG_PS2MULT */
+
+/* ---------------------------------------------------------------------------- */
+/* HMI10 specific stuff                                                                */
+/* ---------------------------------------------------------------------------- */
+#ifdef CONFIG_HMI10
+
+int misc_init_r (void)
+{
+# ifdef CONFIG_IDE_LED
+       volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+       /* Configure PA15 as output port */
+       immap->im_ioport.iop_padir |= 0x0001;
+       immap->im_ioport.iop_paodr |= 0x0001;
+       immap->im_ioport.iop_papar &= ~0x0001;
+       immap->im_ioport.iop_padat &= ~0x0001;  /* turn it off */
+# endif
+       return (0);
+}
+
+# ifdef CONFIG_IDE_LED
+void ide_led (uchar led, uchar status)
+{
+       volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+       /* We have one led for both pcmcia slots */
+       if (status) {                           /* led on */
+               immap->im_ioport.iop_padat |= 0x0001;
+       } else {
+               immap->im_ioport.iop_padat &= ~0x0001;
+       }
+}
+# endif
+#endif /* CONFIG_HMI10 */
+
+/* ---------------------------------------------------------------------------- */
+/* NSCU specific stuff                                                         */
+/* ---------------------------------------------------------------------------- */
+#ifdef CONFIG_NSCU
+
+int misc_init_r (void)
+{
+       volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+       /* wake up ethernet module */
+       immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin       */
+       immr->im_ioport.iop_pcdir |=  0x0004; /* output         */
+       immr->im_ioport.iop_pcso  &= ~0x0004; /* for clarity    */
+       immr->im_ioport.iop_pcdat |=  0x0004; /* enable         */
+
+       return (0);
+}
+#endif /* CONFIG_NSCU */
+
+/* ------------------------------------------------------------------------- */