ppc4xx: lwmon5: Change PHY reset sequence for PHY MDIO address latching

[oweals/u-boot.git] / board / tqm834x / tqm834x.c

diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c
index dada6739b6ca7e433eee80f866b9c4fdc9a2b397..7d0b0554840e1edadb03ed130692b9b814f06441 100644 (file)
--- a/board/tqm834x/tqm834x.c
+++ b/board/tqm834x/tqm834x.c
@@ -32,6 +32,8 @@
 #include <asm-ppc/mmu.h>
 #include <pci.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define IOSYNC                 asm("eieio")
 #define ISYNC                  asm("isync")
 #define SYNC                   asm("sync")
@@ -67,7 +69,7 @@ static void set_cs_config(short cs, long config);
 static void set_ddr_config(void);
 
 /* Local variable */
-static volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
+static volatile immap_t *im = (immap_t *)CFG_IMMR;
 
 /**************************************************************************
  * Board initialzation after relocation to RAM. Used to detect the number
@@ -112,7 +114,7 @@ long int initdram (int board_type)
        /* enable DDR controller */
        im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
                SDRAM_CFG_SREN |
-               SDRAM_CFG_SDRAM_TYPE_DDR);
+               SDRAM_CFG_SDRAM_TYPE_DDR1);
        SYNC;
 
        /* size detection */
@@ -142,19 +144,18 @@ int checkboard (void)
        puts("Board: TQM834x\n");
 
 #ifdef CONFIG_PCI
-       DECLARE_GLOBAL_DATA_PTR;
        volatile immap_t * immr;
        u32 w, f;
 
-       immr = (immap_t *)CFG_IMMRBAR;
-       if (!(immr->reset.rcwh & RCWH_PCIHOST)) {
+       immr = (immap_t *)CFG_IMMR;
+       if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) {
                printf("PCI:   NOT in host mode..?!\n");
                return 0;
        }
 
        /* get bus width */
        w = 32;
-       if (immr->reset.rcwh & RCWH_PCI64)
+       if (immr->reset.rcwh & HRCWH_64_BIT_PCI)
                w = 64;
 
        /* get clock */
@@ -387,7 +388,7 @@ static void set_ddr_config(void) {
        /* don't enable DDR controller yet */
        im->ddr.sdram_cfg =
                SDRAM_CFG_SREN |
-               SDRAM_CFG_SDRAM_TYPE_DDR;
+               SDRAM_CFG_SDRAM_TYPE_DDR1;
        SYNC;
 
        /* Set SDRAM mode */
@@ -405,4 +406,30 @@ static void set_ddr_config(void) {
                (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
                (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
        SYNC;
+
+       /* Workaround for DDR6 Erratum
+        * see MPC8349E Device Errata Rev.8, 2/2006
+        * This workaround influences the MPC internal "input enables"
+        * dependent on CAS latency and MPC revision. According to errata
+        * sheet the internal reserved registers for this workaround are
+        * not available from revision 2.0 and up.
+        */
+
+       /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0
+        * (0x200)
+        */
+       if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) {
+
+               /* There is a internal reserved register at IMMRBAR+0x2F00
+                * which has to be written with a certain value defined by
+                * errata sheet.
+                */
+               u32 *reserved_p = (u32 *)((u8 *)im + 0x2f00);
+
+#if defined(DDR_CASLAT_20)
+               *reserved_p = 0x201c0000;
+#else
+               *reserved_p = 0x202c0000;
+#endif
+       }
 }