fsl: Clean up printing of PCI boot info

[oweals/u-boot.git] / board / tqc / tqm85xx / tlb.c

diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c
index 16b102d1e5e2f954ff51a2082a27d75e559289d5..75dd348aa529c7405580d6b288857b71438bd6a9 100644 (file)
--- a/board/tqc/tqm85xx/tlb.c
+++ b/board/tqc/tqm85xx/tlb.c
@@ -80,7 +80,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
         * TLB 4:       256M    Non-cacheable, guarded
         * 0xc0000000   256M    PCI express MEM First half
         */
-       SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
+       SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
                       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
                       0, 4, BOOKE_PAGESZ_256M, 1),
 
@@ -88,8 +88,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
         * TLB 5:       256M    Non-cacheable, guarded
         * 0xd0000000   256M    PCI express MEM Second half
         */
-       SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
-                      CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
+       SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
+                      CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
                       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
                       0, 5, BOOKE_PAGESZ_256M, 1),
 #else /* !CONFIG_PCIE */
@@ -121,12 +121,25 @@ struct fsl_e_tlb_entry tlb_table[] = {
                       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
                       0, 6, BOOKE_PAGESZ_64M, 1),
 
+#if defined(CONFIG_TQM8548_AG) || defined (CONFIG_TQM8548_BE)
+       /*
+        * TLB 7+8:       2G     DDR, cache enabled
+        * 0x00000000     2G     DDR System memory
+        * Without SPD EEPROM configured DDR, this must be setup manually.
+        */
+       SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+                      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+                      0, 7, BOOKE_PAGESZ_1G, 1),
+
+       SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+                      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+                      MAS3_SX | MAS3_SW | MAS3_SR, 0,
+                      0, 8, BOOKE_PAGESZ_1G, 1),
+#else
        /*
         * TLB 7+8:     512M     DDR, cache disabled (needed for memory test)
         * 0x00000000   512M     DDR System memory
         * Without SPD EEPROM configured DDR, this must be setup manually.
-        * Make sure the TLB count at the top of this table is correct.
-        * Likely it needs to be increased by two for these entries.
         */
        SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
                       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
@@ -136,13 +149,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
                       CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
                       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
                       0, 8, BOOKE_PAGESZ_256M, 1),
-
+#endif
 #ifdef CONFIG_PCIE1
        /*
         * TLB 9:        16M    Non-cacheable, guarded
         * 0xef000000    16M    PCI express IO
         */
-       SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
+       SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_BUS,
                       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
                       0, 9, BOOKE_PAGESZ_16M, 1),
 #endif /* CONFIG_PCIE */
@@ -192,7 +205,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
         * TLB 6:       256M    Non-cacheable, guarded
         * 0xc0000000   256M    PCI express MEM First half
         */
-       SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
+       SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
                       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
                       0, 6, BOOKE_PAGESZ_256M, 1),
 #else /* !CONFIG_PCIE */