MPC85xx: TQM8548: fix SDRAM timing for 533 MHz

[oweals/u-boot.git] / board / tqc / tqm85xx / sdram.c

diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c
index 442ff667c0e1b9d8fc0c6b18b80b0a4293e22fde..09f7c9bba113f56108cb9ad44be503ea764ae488 100644 (file)
--- a/board/tqc/tqm85xx/sdram.c
+++ b/board/tqc/tqm85xx/sdram.c
@@ -66,9 +66,9 @@ int cas_latency (void);
 long int sdram_setup (int casl)
 {
        int i;
-       volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
+       volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 #ifdef CONFIG_TQM8548
-       volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+       volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #else /* !CONFIG_TQM8548 */
        unsigned long cfg_ddr_timing1;
        unsigned long cfg_ddr_mode;
@@ -81,21 +81,23 @@ long int sdram_setup (int casl)
        ddr->sdram_cfg = 0;
 
 #ifdef CONFIG_TQM8548
+       /* Timing and refresh settings for DDR2-533 and below */
+
        ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
        ddr->cs0_config = ddr_cs_conf[0].reg;
-       ddr->timing_cfg_3 = 0x00010000;
+       ddr->timing_cfg_3 = 0x00020000;
 
        /* TIMING CFG 1, 533MHz
         * PRETOACT: 4 Clocks
         * ACTTOPRE: 12 Clocks
         * ACTTORW:  4 Clocks
         * CASLAT:   4 Clocks
-        * REFREC:   34 Clocks
+        * REFREC:   EXT_REFREC:REFREC 53 Clocks
         * WRREC:    4 Clocks
         * ACTTOACT: 3 Clocks
         * WRTORD:   2 Clocks
         */
-       ddr->timing_cfg_1 = 0x4C47A432;
+       ddr->timing_cfg_1 = 0x4C47D432;
 
        /* TIMING CFG 2, 533MHz
         * ADD_LAT:       3 Clocks
@@ -103,10 +105,10 @@ long int sdram_setup (int casl)
         * WR_LAT:        3 Clocks
         * RD_TO_PRE:     2 Clocks
         * WR_DATA_DELAY: 1/2 Clock
-        * CKE_PLS:       1 Clock
-        * FOUR_ACT:      13 Clocks
+        * CKE_PLS:       3 Clock
+        * FOUR_ACT:      14 Clocks
         */
-       ddr->timing_cfg_2 = 0x3318484D;
+       ddr->timing_cfg_2 = 0x331848CE;
 
        /* DDR SDRAM Mode, 533MHz
         * MRS:          Extended Mode Register
@@ -286,7 +288,7 @@ void board_add_ram_info (int use_default)
        }
 }
 
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
        long dram_size = 0;
        int casl;
@@ -296,7 +298,7 @@ long int initdram (int board_type)
         * This DLL-Override only used on TQM8540 and TQM8560
         */
        {
-               volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+               volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
                int i, x;
 
                x = 10;
@@ -336,11 +338,11 @@ long int initdram (int board_type)
        return dram_size;
 }
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-       uint *pstart = (uint *) CFG_MEMTEST_START;
-       uint *pend = (uint *) CFG_MEMTEST_END;
+       uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+       uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
        uint *p;
 
        printf ("SDRAM test phase 1:\n");