sifive: fix palmer's email address

[oweals/u-boot.git] / board / ti / ks2_evm / ddr3_k2hk.c

diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c
index 21a5a0a252e5096b9bbd4dbfb7873b3e781736e9..198c5da0e62204a471080da230e4a69d0eaf1199 100644 (file)
--- a/board/ti/ks2_evm/ddr3_k2hk.c
+++ b/board/ti/ks2_evm/ddr3_k2hk.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Keystone2: DDR3 initialization
  *
  * (C) Copyright 2012-2014
  *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #include <common.h>
@@ -15,70 +14,54 @@
 struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
 struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
 
-void ddr3_init(void)
+u32 ddr3_init(void)
 {
-       char dimm_name[32];
+       u32 ddr3_size;
+       struct ddr3_spd_cb spd_cb;
 
-       ddr3_get_dimm_params(dimm_name);
+       if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
+               printf("Sorry, I don't know how to configure DDR3A.\n"
+                      "Bye :(\n");
+               for (;;)
+                       ;
+       }
 
-       printf("Detected SO-DIMM [%s]\n", dimm_name);
+       printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
 
-       if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
-               init_pll(&ddr3a_400);
-               if (cpu_revision() > 0) {
-                       if (cpu_revision() > 1) {
-                               /* PG 2.0 */
-                               /* Reset DDR3A PHY after PLL enabled */
-                               ddr3_reset_ddrphy();
-                               ddr3phy_1600_8g.zq0cr1 |= 0x10000;
-                               ddr3phy_1600_8g.zq1cr1 |= 0x10000;
-                               ddr3phy_1600_8g.zq2cr1 |= 0x10000;
-                               ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
-                                                &ddr3phy_1600_8g);
-                       } else {
-                               /* PG 1.1 */
-                               ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
-                                                &ddr3phy_1600_8g);
-                       }
+       if ((cpu_revision() > 1) ||
+           (__raw_readl(KS2_RSTCTRL_RSTYPE) & 0x1)) {
+               printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
+               if (spd_cb.ddrspdclock == 1600)
+                       init_pll(&ddr3a_400);
+               else
+                       init_pll(&ddr3a_333);
+       }
 
-                       ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
-                                         &ddr3_1600_8g);
-                       printf("DRAM:  Capacity 8 GiB (includes reported below)\n");
-               } else {
-                       ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
-                       ddr3_1600_8g.sdcfg |= 0x1000;
-                       ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
-                                         &ddr3_1600_8g);
-                       printf("DRAM:  Capacity 4 GiB (includes reported below)\n");
-               }
-       } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
-               init_pll(&ddr3a_333);
-               if (cpu_revision() > 0) {
-                       if (cpu_revision() > 1) {
-                               /* PG 2.0 */
-                               /* Reset DDR3A PHY after PLL enabled */
-                               ddr3_reset_ddrphy();
-                               ddr3phy_1333_2g.zq0cr1 |= 0x10000;
-                               ddr3phy_1333_2g.zq1cr1 |= 0x10000;
-                               ddr3phy_1333_2g.zq2cr1 |= 0x10000;
-                               ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
-                                                &ddr3phy_1333_2g);
-                       } else {
-                               /* PG 1.1 */
-                               ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
-                                                &ddr3phy_1333_2g);
-                       }
-                       ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
-                                         &ddr3_1333_2g);
-               } else {
-                       ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
-                       ddr3_1333_2g.sdcfg |= 0x1000;
-                       ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
-                                         &ddr3_1333_2g);
+       if (cpu_revision() > 0) {
+               if (cpu_revision() > 1) {
+                       /* PG 2.0 */
+                       /* Reset DDR3A PHY after PLL enabled */
+                       ddr3_reset_ddrphy();
+                       spd_cb.phy_cfg.zq0cr1 |= 0x10000;
+                       spd_cb.phy_cfg.zq1cr1 |= 0x10000;
+                       spd_cb.phy_cfg.zq2cr1 |= 0x10000;
                }
+               ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
+
+               ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
+
+               ddr3_size = spd_cb.ddr_size_gbyte;
        } else {
-               printf("Unknown SO-DIMM. Cannot configure DDR3\n");
-               while (1)
-                       ;
+               ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
+               spd_cb.emif_cfg.sdcfg |= 0x1000;
+               ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
+               ddr3_size = spd_cb.ddr_size_gbyte / 2;
        }
+       printf("DRAM: %d GiB (includes reported below)\n", ddr3_size);
+
+       /* Apply the workaround for PG 1.0 and 1.1 Silicons */
+       if (cpu_revision() <= 1)
+               ddr3_err_reset_workaround();
+
+       return ddr3_size;
 }