board: ti: am335x: Add platdata for cpsw in SPL

[oweals/u-boot.git] / board / ti / ks2_evm / ddr3_k2e.c

diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c
index 35ffb4205673f3f63295e4acaeb3a29f00fc6d0d..95fe3a9021e237c2e4eca5819ce97ee82dc3ab8d 100644 (file)
--- a/board/ti/ks2_evm/ddr3_k2e.c
+++ b/board/ti/ks2_evm/ddr3_k2e.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Keystone2: DDR3 initialization
  *
- * (C) Copyright 2014
+ * (C) Copyright 2014-2015
  *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #include <common.h>
@@ -12,42 +11,37 @@
 #include <asm/arch/ddr3.h>
 
 static struct pll_init_data ddr3_400 = DDR3_PLL_400;
+static struct pll_init_data ddr3_333 = DDR3_PLL_333;
 
 u32 ddr3_init(void)
 {
-       u32 ddr3_size;
-       char dimm_name[32];
+       struct ddr3_spd_cb spd_cb;
 
-       if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1))
-               init_pll(&ddr3_400);
+       if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
+               printf("Sorry, I don't know how to configure DDR3A.\n"
+                      "Bye :(\n");
+               for (;;)
+                       ;
+       }
 
-       ddr3_get_dimm_params(dimm_name);
+       printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
 
-       printf("Detected SO-DIMM [%s]\n", dimm_name);
+       printf("DDR3 speed %d\n", spd_cb.ddrspdclock);
+       if (spd_cb.ddrspdclock == 1600)
+               init_pll(&ddr3_400);
+       else
+               init_pll(&ddr3_333);
 
        /* Reset DDR3 PHY after PLL enabled */
        ddr3_reset_ddrphy();
 
-       if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) {
-               /* 8G SO-DIMM */
-               ddr3_size = 8;
-               printf("DRAM: 8 GiB\n");
-               ddr3phy_1600_8g.zq0cr1 |= 0x10000;
-               ddr3phy_1600_8g.zq1cr1 |= 0x10000;
-               ddr3phy_1600_8g.zq2cr1 |= 0x10000;
-               ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
-               ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g);
-       } else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) {
-               /* 4G SO-DIMM */
-               ddr3_size = 4;
-               printf("DRAM: 4 GiB\n");
-               ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g);
-               ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g);
-       } else {
-               printf("Unknown SO-DIMM. Cannot configure DDR3\n");
-               while (1)
-                       ;
-       }
+       spd_cb.phy_cfg.zq0cr1 |= 0x10000;
+       spd_cb.phy_cfg.zq1cr1 |= 0x10000;
+       spd_cb.phy_cfg.zq2cr1 |= 0x10000;
+       ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg);
+       ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg);
+
+       printf("DRAM: %d GiB\n", spd_cb.ddr_size_gbyte);
 
-       return ddr3_size;
+       return (u32)spd_cb.ddr_size_gbyte;
 }