DECLARE_GLOBAL_DATA_PTR;
-unsigned int external_clk[ext_clk_count] = {
- [sys_clk] = 122880000,
- [alt_core_clk] = 100000000,
- [pa_clk] = 122880000,
- [tetris_clk] = 122880000,
- [ddr3_clk] = 100000000,
- [pcie_clk] = 100000000,
- [sgmii_clk] = 156250000,
- [usb_clk] = 100000000,
-};
+unsigned int get_external_clk(u32 clk)
+{
+ unsigned int clk_freq;
+
+ switch (clk) {
+ case sys_clk:
+ clk_freq = 122880000;
+ break;
+ case alt_core_clk:
+ clk_freq = 100000000;
+ break;
+ case pa_clk:
+ clk_freq = 122880000;
+ break;
+ case tetris_clk:
+ clk_freq = 122880000;
+ break;
+ case ddr3a_clk:
+ clk_freq = 100000000;
+ break;
+ default:
+ clk_freq = 0;
+ break;
+ }
+
+ return clk_freq;
+}
static struct pll_init_data core_pll_config[NUM_SPDS] = {
[SPD800] = CORE_PLL_799,
[SPD1000] = CORE_PLL_1000,
- [SPD800] = CORE_PLL_1198,
+ [SPD1200] = CORE_PLL_1198,
};
s16 divn_val[16] = {
switch (pll) {
case MAIN_PLL:
- speed = get_max_dev_speed();
+ speed = get_max_dev_speed(speeds);
data = &core_pll_config[speed];
break;
case TETRIS_PLL:
- speed = get_max_arm_speed();
+ speed = get_max_arm_speed(speeds);
data = &tetris_pll_config[speed];
break;
case PASS_PLL:
.phy_addr = 0,
.slave_port = 1,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
+ .phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2L_EMAC1",
.phy_addr = 1,
.slave_port = 2,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
+ .phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2L_EMAC2",
.phy_addr = 2,
.slave_port = 3,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ .phy_if = PHY_INTERFACE_MODE_SGMII,
},
{
.int_name = "K2L_EMAC3",
.phy_addr = 3,
.slave_port = 4,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ .phy_if = PHY_INTERFACE_MODE_SGMII,
},
};
}
#endif
+#if defined(CONFIG_MULTI_DTB_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ if (!strcmp(name, "keystone-k2l-evm"))
+ return 0;
+
+ return -1;
+}
+#endif
+
#ifdef CONFIG_SPL_BUILD
void spl_init_keystone_plls(void)
{