Merge git://git.denx.de/u-boot

[oweals/u-boot.git] / board / ti / am43xx / mux.c

diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index 51f7fd61d5ceff525cb5600121c99bc1e5b23602..510477dad9e29f8e3419ccf5f89c199d4d9e4000 100644 (file)
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -11,6 +11,41 @@
 #include <asm/arch/mux.h>
 #include "board.h"
 
+static struct module_pin_mux rmii1_pin_mux[] = {
+       {OFFSET(mii1_txen), MODE(1)},                   /* RMII1_TXEN */
+       {OFFSET(mii1_txd1), MODE(1)},                   /* RMII1_TD1 */
+       {OFFSET(mii1_txd0), MODE(1)},                   /* RMII1_TD0 */
+       {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},        /* RMII1_RD1 */
+       {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},        /* RMII1_RD0 */
+       {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE},        /* RMII1_RXDV */
+       {OFFSET(mii1_crs), MODE(1) | RXACTIVE},         /* RMII1_CRS_DV */
+       {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},       /* RMII1_RXERR */
+       {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},     /* RMII1_refclk */
+       {-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+       {OFFSET(mii1_txen), MODE(2)},                   /* RGMII1_TCTL */
+       {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},        /* RGMII1_RCTL */
+       {OFFSET(mii1_txd3), MODE(2)},                   /* RGMII1_TD3 */
+       {OFFSET(mii1_txd2), MODE(2)},                   /* RGMII1_TD2 */
+       {OFFSET(mii1_txd1), MODE(2)},                   /* RGMII1_TD1 */
+       {OFFSET(mii1_txd0), MODE(2)},                   /* RGMII1_TD0 */
+       {OFFSET(mii1_txclk), MODE(2)},                  /* RGMII1_TCLK */
+       {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},       /* RGMII1_RCLK */
+       {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},        /* RGMII1_RD3 */
+       {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},        /* RGMII1_RD2 */
+       {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},        /* RGMII1_RD1 */
+       {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},        /* RGMII1_RD0 */
+       {-1},
+};
+
+static struct module_pin_mux mdio_pin_mux[] = {
+       {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+       {OFFSET(mdio_clk), MODE(0) | PULLUP_EN},        /* MDIO_CLK */
+       {-1},
+};
+
 static struct module_pin_mux uart0_pin_mux[] = {
        {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
        {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
@@ -38,6 +73,47 @@ static struct module_pin_mux gpio5_7_pin_mux[] = {
        {-1},
 };
 
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+       {OFFSET(gpmc_ad0),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
+       {OFFSET(gpmc_ad1),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
+       {OFFSET(gpmc_ad2),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
+       {OFFSET(gpmc_ad3),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
+       {OFFSET(gpmc_ad4),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
+       {OFFSET(gpmc_ad5),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
+       {OFFSET(gpmc_ad6),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
+       {OFFSET(gpmc_ad7),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+       {OFFSET(gpmc_ad8),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8  */
+       {OFFSET(gpmc_ad9),      (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9  */
+       {OFFSET(gpmc_ad10),     (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
+       {OFFSET(gpmc_ad11),     (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
+       {OFFSET(gpmc_ad12),     (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
+       {OFFSET(gpmc_ad13),     (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
+       {OFFSET(gpmc_ad14),     (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
+       {OFFSET(gpmc_ad15),     (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
+#endif
+       {OFFSET(gpmc_wait0),    (MODE(0) | RXACTIVE | PULLUP_EN)}, /* Wait */
+       {OFFSET(gpmc_wpn),      (MODE(7) | PULLUP_EN)}, /* Write Protect */
+       {OFFSET(gpmc_csn0),     (MODE(0) | PULLUP_EN)}, /* Chip-Select */
+       {OFFSET(gpmc_wen),      (MODE(0) | PULLDOWN_EN)}, /* Write Enable */
+       {OFFSET(gpmc_oen_ren),  (MODE(0) | PULLDOWN_EN)}, /* Read Enable */
+       {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* Addr Latch Enable*/
+       {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* Byte Enable */
+       {-1},
+};
+#endif
+
+static __maybe_unused struct module_pin_mux qspi_pin_mux[] = {
+       {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
+       {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
+       {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */
+       {OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */
+       {OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */
+       {OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */
+       {-1},
+};
+
 void enable_uart0_pin_mux(void)
 {
        configure_module_pin_mux(uart0_pin_mux);
@@ -47,9 +123,28 @@ void enable_board_pin_mux(void)
 {
        configure_module_pin_mux(mmc0_pin_mux);
        configure_module_pin_mux(i2c0_pin_mux);
+       configure_module_pin_mux(mdio_pin_mux);
 
-       if (board_is_gpevm())
+       if (board_is_gpevm()) {
                configure_module_pin_mux(gpio5_7_pin_mux);
+               configure_module_pin_mux(rgmii1_pin_mux);
+#if defined(CONFIG_NAND)
+               configure_module_pin_mux(nand_pin_mux);
+#endif
+       } else if (board_is_sk() || board_is_idk()) {
+               configure_module_pin_mux(rgmii1_pin_mux);
+#if defined(CONFIG_NAND)
+               printf("Error: NAND flash not present on this board\n");
+#endif
+               configure_module_pin_mux(qspi_pin_mux);
+       } else if (board_is_eposevm()) {
+               configure_module_pin_mux(rmii1_pin_mux);
+#if defined(CONFIG_NAND)
+               configure_module_pin_mux(nand_pin_mux);
+#else
+               configure_module_pin_mux(qspi_pin_mux);
+#endif
+       }
 }
 
 void enable_i2c0_pin_mux(void)