#ifndef _BOARD_H_
#define _BOARD_H_
+/**
+ * AM335X (EMIF_4D) EMIF REG_COS_COUNT_1, REG_COS_COUNT_2, and
+ * REG_PR_OLD_COUNT values to avoid LCDC DMA FIFO underflows and Frame
+ * Synchronization Lost errors. The values are the biggest that work
+ * reliably with offered video modes and the memory subsystem on the
+ * boards. These register have are briefly documented in "7.3.3.5.2
+ * Command Starvation" section of AM335x TRM. The REG_COS_COUNT_1 and
+ * REG_COS_COUNT_2 do not have any effect on current versions of
+ * AM335x.
+ */
+#define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK 0x00141414
+#define EMIF_OCP_CONFIG_AM335X_EVM 0x003d3d3d
+
static inline int board_is_bone(void)
{
return board_ti_is("A335BONE");
return board_is_bone_lt() && !strncmp(board_ti_get_rev(), "BBG1", 4);
}
+static inline int board_is_beaglebonex(void)
+{
+ return board_is_bone() || board_is_bone_lt() || board_is_bbg1();
+}
+
static inline int board_is_evm_sk(void)
{
return board_ti_is("A335X_SK");
strncmp("1.5", board_ti_get_rev(), 3) <= 0);
}
+static inline int board_is_icev2(void)
+{
+ return board_ti_is("A335_ICE") && !strncmp("2", board_ti_get_rev(), 1);
+}
+
/*
* We have three pin mux functions that must exist. We must be able to enable
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a