arm: mach-k3: Enable dcache in SPL

[oweals/u-boot.git] / board / theadorable / theadorable.c

diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c
index 7b9c706cd47bf9229e6a011aa1deb34b5805d409..621e26905ba72d1859894abf6fbb505757d29573 100644 (file)
--- a/board/theadorable/theadorable.c
+++ b/board/theadorable/theadorable.c
@@ -6,6 +6,7 @@
 #include <common.h>
 #include <console.h>
 #include <i2c.h>
+#include <init.h>
 #include <pci.h>
 #if !defined(CONFIG_SPL_BUILD)
 #include <bootcount.h>
@@ -14,11 +15,11 @@
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
-#include <linux/crc8.h>
 #include <linux/mbus.h>
 #ifdef CONFIG_NET
 #include <netdev.h>
 #endif
+#include <u-boot/crc.h>
 #include "theadorable.h"
 
 #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
@@ -132,15 +133,15 @@ MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
        return &board_ddr_modes[0];
 }
 
-MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
+MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
 {
        return &theadorable_serdes_cfg[0];
 }
 
 u8 board_sat_r_get(u8 dev_num, u8 reg)
 {
-       /* Bit 0 enables PCI 2.0 link capabilities instead of PCI 1.x */
-       return 0x01;
+       /* Bit x enables PCI 2.0 link capabilities instead of PCI 1.x */
+       return 0xe;     /* PEX port 0 is PCIe Gen1, PEX port 1..3 PCIe Gen2 */
 }
 
 int board_early_init_f(void)