ppc4xx: lwmon5: Change PHY reset sequence for PHY MDIO address latching
[oweals/u-boot.git] / board / stxxtc / stxxtc.c
index b38b4bea47409f2880204f2ebef5f6d1861a4732..87a2022761384a5b37d5b1779035daef54b47161 100644 (file)
@@ -481,12 +481,12 @@ void reset_phys(void)
        mii_init();
 
        for (phyno = 0; phyno < 32; ++phyno) {
-               miiphy_read(phyno, PHY_PHYIDR1, &v);
+               miiphy_read("FEC ETHERNET", phyno, PHY_PHYIDR1, &v);
                if (v == 0xFFFF)
                        continue;
-               miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
+               miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_POWD);
                udelay(10000);
-               miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
+               miiphy_write("FEC ETHERNET", phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
                udelay(10000);
        }
 }
@@ -574,9 +574,9 @@ int board_early_init_f(void)
        return 0;
 }
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+#if defined(CONFIG_CMD_NAND)
 
-#include <linux/mtd/nand.h>
+#include <linux/mtd/nand_legacy.h>
 
 extern ulong nand_probe(ulong physadr);
 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];