projects / oweals / u-boot.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
Reworked FSL Book-E TLB macros to be more readable
[oweals/u-boot.git] / board / stxssa / init.S
diff --git a/board/stxssa/init.S b/board/stxssa/init.S
index a1a8d9e0cbbf9473ee8f4f3ab13e846ff24c86b8..82dafb80b88a90e2171accf9988d1177588166d6 100644 (file)
--- a/board/stxssa/init.S
+++ b/board/stxssa/init.S
@@ -49,7 +49,7 @@
  *
  * MAS0: tlbsel, esel, nv
  * MAS1: valid, iprot, tid, ts, tsize
- * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS2: epn, x0, x1, w, i, m, g, e
  * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
  */
 
@@ -81,10 +81,10 @@ tlb1_entry:
         * This ends up at a TLB0 Index==0 entry, and must not collide
         * with other TLB0 Entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 #else
 #error("Update the number of table entries in tlb1_entry")
 #endif
@@ -100,33 +100,25 @@ tlb1_entry:
         * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
         * and must not collide with other TLB0 entries.
         */
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), \
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), \
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), \
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), \
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
-       .long TLB1_MAS0(0, 0, 0)
-       .long TLB1_MAS1(1, 0, 0, 0, 0)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
-                       0,0,0,0,0,0,0,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), \
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(0, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
+       .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
+       .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
 
        /*
@@ -134,50 +126,46 @@ tlb1_entry:
         * 0xfc000000   6M4     FLASH
         * Out of reset this entry is only 4K.
         */
-       .long TLB1_MAS0(1, 0, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 0, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 1:       256M    Non-cacheable, guarded
         * 0x80000000   256M    PCI1 MEM First half
         */
-       .long TLB1_MAS0(1, 1, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 1, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 2:       256M    Non-cacheable, guarded
         * 0x90000000   256M    PCI1 MEM Second half
         */
-       .long TLB1_MAS0(1, 2, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), \
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), \
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 2, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 3:       256M    Non-cacheable, guarded
         * 0xa0000000   256M    PCI2 MEM First half
         */
-       .long TLB1_MAS0(1, 3, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 3, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 4:       256M    Non-cacheable, guarded
         * 0xb0000000   256M    PCI2 MEM Second half
         */
-       .long TLB1_MAS0(1, 4, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), \
-                       0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), \
-                       0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 4, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 5:       64M     Non-cacheable, guarded
@@ -185,10 +173,10 @@ tlb1_entry:
         * 0xe200_0000  16M     PCI1 IO
         * 0xe300_0000  16M     PCI2 IO
         */
-       .long TLB1_MAS0(1, 5, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 5, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+       .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
 
        /*
         * TLB 6:       256M    Non-cacheable, guarded
@@ -196,10 +184,10 @@ tlb1_entry:
         * 0xfb000000           Configuration Latch register (one word)
         * 0xfc000000           Up to 64M flash
         */
-       .long TLB1_MAS0(1, 7, 0)
-       .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-       .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_OPTION_BASE), 0,0,0,0,1,0,1,0)
-       .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_OPTION_BASE), 0,0,0,0,0,1,0,1,0,1)
+       .long FSL_BOOKE_MAS0(1, 7, 0)
+       .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+       .long FSL_BOOKE_MAS2(CFG_LBC_OPTION_BASE, (MAS2_I|MAS2_G))
+       .long FSL_BOOKE_MAS3(CFG_LBC_OPTION_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
        entry_end
 
 /*
Unnamed repository; edit this file 'description' to name the repository.