/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
* Check Bank 0 Memory Size for re-configuration
*/
#if PCU_E_WITH_SWAPPED_CS /* XXX */
- size_b0 = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
+ size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
#else /* XXX */
- size_b0 = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+ size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
#endif /* XXX */
memctl->memc_mamr = CFG_MAMR | MAMR_PTAE;
/* Configure all needed port pins for GPIO */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
-# if CFG_ETH_MDDIS_VALUE
+# ifdef CFG_ETH_MDDIS_VALUE
immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS;
# else
immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS); /* Set low */
/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
#if !PCU_E_WITH_SWAPPED_CS
-# if CFG_ETH_MDDIS_VALUE
+# ifdef CFG_ETH_MDDIS_VALUE
value |= CFG_PB_ETH_MDDIS;
# else
value &= ~(CFG_PB_ETH_MDDIS);
# endif
#endif
-#if CFG_ETH_CFG1_VALUE
+#ifdef CFG_ETH_CFG1_VALUE
value |= CFG_PB_ETH_CFG1;
#else
value &= ~(CFG_PB_ETH_CFG1);
#endif
-#if CFG_ETH_CFG2_VALUE
+#ifdef CFG_ETH_CFG2_VALUE
value |= CFG_PB_ETH_CFG2;
#else
value &= ~(CFG_PB_ETH_CFG2);
#endif
-#if CFG_ETH_CFG3_VALUE
+#ifdef CFG_ETH_CFG3_VALUE
value |= CFG_PB_ETH_CFG3;
#else
value &= ~(CFG_PB_ETH_CFG3);
/*-----------------------------------------------------------------------
* Board Special Commands: access functions for "PUMA" FPGA
*/
-#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+#if defined(CONFIG_CMD_BSP)
#define PUMA_READ_MODE 0
#define PUMA_LOAD_MODE 1
"status - print PUMA status\n"
"puma load addr len - load PUMA configuration data\n");
-#endif /* CFG_CMD_BSP */
+#endif
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */