vision2: Remove unused get_board_rev function

[oweals/u-boot.git] / board / sbc8548 / tlb.c

diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index a0b4e36e7b030fb47943ce40ff93ea42bce3b002..bb4c05210cc8f5753299c46d93b1fb07ab77e05c 100644 (file)
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -56,51 +56,43 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      0, 0, BOOKE_PAGESZ_64M, 1),
 
        /*
-        * TLB 1:       256M    Non-cacheable, guarded
-        * 0x80000000   256M    PCI1 MEM First half
+        * TLB 1:       1G      Non-cacheable, guarded
+        * 0x80000000   512M    PCI1 MEM
+        * 0xa0000000   512M    PCIe MEM
         */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                     0, 1, BOOKE_PAGESZ_256M, 1),
+                     0, 1, BOOKE_PAGESZ_1G, 1),
 
        /*
-        * TLB 2:       256M    Non-cacheable, guarded
-        * 0x90000000   256M    PCI1 MEM Second half
+        * TLB 2:       64M     Non-cacheable, guarded
+        * 0xe0000000   1M      CCSRBAR
+        * 0xe2000000   8M      PCI1 IO
+        * 0xe2800000   8M      PCIe IO
         */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
-                     CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+       SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                     0, 2, BOOKE_PAGESZ_256M, 1),
+                     0, 2, BOOKE_PAGESZ_64M, 1),
 
        /*
-        * TLB 3:       256M Cacheable, non-guarded
-        * 0x0          256M DDR SDRAM
+        * TLB 3:       64M     Cacheable, non-guarded
+        * 0xf0000000   64M     LBC SDRAM First half
         */
-       #if !defined(CONFIG_SPD_EEPROM)
-       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+       SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-                     0, 3, BOOKE_PAGESZ_256M, 1),
-       #endif
-
-       /*
-        * TLB 4:       64M     Non-cacheable, guarded
-        * 0xe0000000   1M      CCSRBAR
-        * 0xe2000000   16M     PCI1 IO
-        */
-       SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                     0, 4, BOOKE_PAGESZ_64M, 1),
+                     0, 3, BOOKE_PAGESZ_64M, 1),
 
        /*
-        * TLB 5:       64M     Cacheable, non-guarded
-        * 0xf0000000   64M     LBC SDRAM
+        * TLB 4:       64M     Cacheable, non-guarded
+        * 0xf4000000   64M     LBC SDRAM Second half
         */
-       SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
+       SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
+                     CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
                      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-                     0, 5, BOOKE_PAGESZ_64M, 1),
+                     0, 4, BOOKE_PAGESZ_64M, 1),
 
        /*
-        * TLB 6:       16M     Cacheable, non-guarded
+        * TLB 5:       16M     Cacheable, non-guarded
         * 0xf8000000   1M      7-segment LED display
         * 0xf8100000   1M      User switches
         * 0xf8300000   1M      Board revision
@@ -108,24 +100,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
         */
        SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                     0, 6, BOOKE_PAGESZ_16M, 1),
+                     0, 5, BOOKE_PAGESZ_16M, 1),
 
        /*
-        * TLB 7:       4M      Non-cacheable, guarded
+        * TLB 6:       4M      Non-cacheable, guarded
         * 0xfb800000   4M      1st 4MB block of 64MB user FLASH
         */
        SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                     0, 7, BOOKE_PAGESZ_4M, 1),
+                     0, 6, BOOKE_PAGESZ_4M, 1),
 
        /*
-        * TLB 8:       4M      Non-cacheable, guarded
+        * TLB 7:       4M      Non-cacheable, guarded
         * 0xfbc00000   4M      2nd 4MB block of 64MB user FLASH
         */
        SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
                      CONFIG_SYS_ALT_FLASH + 0x400000,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-                     0, 8, BOOKE_PAGESZ_4M, 1),
+                     0, 7, BOOKE_PAGESZ_4M, 1),
 
 };