#define MCLK_DIVISOR 4 /* SCLK = MCLK / MCLK_DIVISOR */
#define SCLK_DIVISOR (Daq64xSampling ? 64 : 128)
- /* LRCLK = SCLK / SCLK_DIVISOR */
+ /* LRCLK = SCLK / SCLK_DIVISOR */
#define TIGHTEN_UP_BRG_EN_TIMING /* Tighten up the BRG enable timing */
#define RUN_SCLK_ON_BRG_INT /* Run SCLK on BRG_INT instead of MCLK */
- /* The 8260 (Mask B.3) seems to have */
- /* problems generating SCLK from MCLK */
+ /* The 8260 (Mask B.3) seems to have */
+ /* problems generating SCLK from MCLK */
/* via CLK9. */
#define RUN_LRCLK_ON_BRG_INT /* Run LRCLK on BRG_INT instead of SCLK */
- /* The 8260 (Mask B.3) seems to have */
- /* problems generating LRCLK from SCLK */
+ /* The 8260 (Mask B.3) seems to have */
+ /* problems generating LRCLK from SCLK */
+
+#define NUM_LRCLKS_TO_STABILIZE 1 /* Number of LRCLK period (sample) */
+ /* to wait for the clock to stabilize */
#define CPM_CLK (gd->bd->bi_cpmfreq)
#define DFBRG 4
#define BRG_INT_CLK (CPM_CLK * 2 / DFBRG)
- /* BRG = CPM * 2 / DFBRG (Sect 9.8) */
- /* BRG = CPM * 2 / 4 */
- /* BRG = CPM / 2 */
+ /* BRG = CPM * 2 / DFBRG (Sect 9.8) */
+ /* BRG = CPM * 2 / 4 */
+ /* BRG = CPM / 2 */
#define CPM_BRG_EXTC_MASK ((uint)0x0000C000)
#define CPM_BRG_EXTC_SHIFT 14
#define CPM_BRG_EXTC_CLK5 2
#define CPM_BRG_EXTC_CLK15 CPM_BRG_EXTC_CLK5
+#define IM_BRGC1 ((uint *)0xf00119f0)
+#define IM_BRGC2 ((uint *)0xf00119f4)
+#define IM_BRGC3 ((uint *)0xf00119f8)
+#define IM_BRGC4 ((uint *)0xf00119fc)
+#define IM_BRGC5 ((uint *)0xf00115f0)
+#define IM_BRGC6 ((uint *)0xf00115f4)
+#define IM_BRGC7 ((uint *)0xf00115f8)
+#define IM_BRGC8 ((uint *)0xf00115fc)
+
/*
* External declarations
*/
extern uint Daq_BRG_Rate(uint brg);
extern uint Daq_Get_SampleRate(void);
-extern uint Daq_Set_SampleRate(uint rate, uint force);
extern void Daq_Init_Clocks(int sample_rate, int sample_64x);
extern void Daq_Stop_Clocks(void);