/*
* board/renesas/salvator-x/salvator-x.c
- * This file is Salvator-X board support.
+ * This file is Salvator-X/Salvator-XS board support.
*
* Copyright (C) 2015-2017 Renesas Electronics Corporation
* Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#define TMU0_MSTP125 BIT(25) /* secure */
#define TMU1_MSTP124 BIT(24) /* non-secure */
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
-#define SD0_MSTP314 BIT(14)
-#define SD1_MSTP313 BIT(13)
-#define SD2_MSTP312 BIT(12) /* either MMC0 */
-#define SD3_MSTP311 BIT(11) /* either MMC1 */
-
-#define SD0CKCR 0xE6150074
-#define SD1CKCR 0xE6150078
-#define SD2CKCR 0xE6150268
-#define SD3CKCR 0xE615026C
+#define DVFS_MSTP926 BIT(26)
+#define HSUSB_MSTP704 BIT(4) /* HSUSB */
int board_early_init_f(void)
{
/* TMU0,1 */ /* which use ? */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
- /* SCIF2 */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
- /* eMMC */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD1_MSTP313 | SD2_MSTP312);
- /* SDHI0, 3 */
- mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314 | SD3_MSTP311);
-
- writel(0, SD0CKCR);
- writel(0, SD1CKCR);
- writel(0, SD2CKCR);
- writel(0, SD3CKCR);
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+ /* DVFS for reset */
+ mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+#endif
return 0;
}
/* -/W 32 Power resume control register 2 (3DG) */
#define SYSC_PWRONCR2 0xE618010C
+/* HSUSB block registers */
+#define HSUSB_REG_LPSTS 0xE6590102
+#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
+#define HSUSB_REG_UGCTRL2 0xE6590184
+#define HSUSB_REG_UGCTRL2_USB0SEL 0x30
+#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
+
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
- /* Init PFC controller */
- r8a7795_pinmux_init();
-
+#if defined(CONFIG_R8A7795)
/* GSX: force power and clock supply */
writel(0x0000001F, SYSC_PWRONCR2);
while (readl(SYSC_PWRSR2) != 0x000003E0)
mdelay(20);
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
+#endif
+
+ /* USB1 pull-up */
+ setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
+
+ /* Configure the HSUSB block */
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+ /* Choice USB0SEL */
+ clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
+ HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
+ /* low power status */
+ setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
return 0;
}
-#ifdef CONFIG_SH_SDHI
-int board_mmc_init(bd_t *bis)
+int dram_init(void)
{
- int ret = -ENODEV;
-
- /* SDHI0 */
- gpio_request(GPIO_GFN_SD0_DAT0, NULL);
- gpio_request(GPIO_GFN_SD0_DAT1, NULL);
- gpio_request(GPIO_GFN_SD0_DAT2, NULL);
- gpio_request(GPIO_GFN_SD0_DAT3, NULL);
- gpio_request(GPIO_GFN_SD0_CLK, NULL);
- gpio_request(GPIO_GFN_SD0_CMD, NULL);
- gpio_request(GPIO_GFN_SD0_CD, NULL);
- gpio_request(GPIO_GFN_SD0_WP, NULL);
-
- gpio_request(GPIO_GP_5_2, NULL);
- gpio_request(GPIO_GP_5_1, NULL);
- gpio_direction_output(GPIO_GP_5_2, 1); /* power on */
- gpio_direction_output(GPIO_GP_5_1, 1); /* 1: 3.3V, 0: 1.8V */
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
- SH_SDHI_QUIRK_64BIT_BUF);
- if (ret)
- return ret;
-
- /* SDHI1/SDHI2 eMMC */
- gpio_request(GPIO_GFN_SD1_DAT0, NULL);
- gpio_request(GPIO_GFN_SD1_DAT1, NULL);
- gpio_request(GPIO_GFN_SD1_DAT2, NULL);
- gpio_request(GPIO_GFN_SD1_DAT3, NULL);
- gpio_request(GPIO_GFN_SD2_DAT0, NULL);
- gpio_request(GPIO_GFN_SD2_DAT1, NULL);
- gpio_request(GPIO_GFN_SD2_DAT2, NULL);
- gpio_request(GPIO_GFN_SD2_DAT3, NULL);
- gpio_request(GPIO_GFN_SD2_CLK, NULL);
- gpio_request(GPIO_GFN_SD2_CMD, NULL);
- gpio_request(GPIO_GP_5_3, NULL);
- gpio_request(GPIO_GP_5_9, NULL);
- gpio_direction_output(GPIO_GP_5_3, 0); /* 1: 3.3V, 0: 1.8V */
- gpio_direction_output(GPIO_GP_5_9, 0); /* 1: 3.3V, 0: 1.8V */
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 1,
- SH_SDHI_QUIRK_64BIT_BUF);
- if (ret)
- return ret;
-
- /* SDHI3 */
- gpio_request(GPIO_GFN_SD3_DAT0, NULL); /* GP_4_9 */
- gpio_request(GPIO_GFN_SD3_DAT1, NULL); /* GP_4_10 */
- gpio_request(GPIO_GFN_SD3_DAT2, NULL); /* GP_4_11 */
- gpio_request(GPIO_GFN_SD3_DAT3, NULL); /* GP_4_12 */
- gpio_request(GPIO_GFN_SD3_CLK, NULL); /* GP_4_7 */
- gpio_request(GPIO_GFN_SD3_CMD, NULL); /* GP_4_8 */
- /* IPSR10 */
- gpio_request(GPIO_FN_SD3_CD, NULL);
- gpio_request(GPIO_FN_SD3_WP, NULL);
-
- gpio_request(GPIO_GP_3_15, NULL);
- gpio_request(GPIO_GP_3_14, NULL);
- gpio_direction_output(GPIO_GP_3_15, 1); /* power on */
- gpio_direction_output(GPIO_GP_3_14, 1); /* 1: 3.3V, 0: 1.8V */
-
- ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI3_BASE, 2,
- SH_SDHI_QUIRK_64BIT_BUF);
- return ret;
-}
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+ gd->ram_size += PHYS_SDRAM_2_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+ gd->ram_size += PHYS_SDRAM_3_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 4)
+ gd->ram_size += PHYS_SDRAM_4_SIZE;
#endif
-int dram_init(void)
-{
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ return 0;
+}
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+ gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+ gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 4)
+ gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+ gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+#endif
return 0;
}
void reset_cpu(ulong addr)
{
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+ i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
+#else
/* only CA57 ? */
writel(RST_CODE, RST_CA57RESCNT);
+#endif
}
-
-static const struct sh_serial_platdata serial_platdata = {
- .base = SCIF2_BASE,
- .type = PORT_SCIF,
- .clk = CONFIG_SH_SCIF_CLK_FREQ,
- .clk_mode = INT_CLK,
-};
-
-U_BOOT_DEVICE(salvator_x_scif2) = {
- .name = "serial_sh",
- .platdata = &serial_platdata,
-};
projects / oweals / u-boot.git / blobdiff