Merge git://git.denx.de/u-boot-fsl-qoriq

[oweals/u-boot.git] / board / renesas / salvator-x / salvator-x.c

diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index 038d6de6109635cce91c979737136e625ba238b3..debd1db7214973ad607c77323b911560c1313f0e 100644 (file)
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -1,8 +1,8 @@
 /*
  * board/renesas/salvator-x/salvator-x.c
- *     This file is Salvator-X board support.
+ *     This file is Salvator-X/Salvator-XS board support.
  *
- * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015-2017 Renesas Electronics Corporation
  * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  *
  * SPDX-License-Identifier: GPL-2.0+
@@ -22,6 +22,7 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/rmobile.h>
 #include <asm/arch/rcar-mstp.h>
+#include <asm/arch/sh_sdhi.h>
 #include <i2c.h>
 #include <mmc.h>
 
@@ -48,14 +49,18 @@ void s_init(void)
 #define TMU0_MSTP125           BIT(25) /* secure */
 #define TMU1_MSTP124           BIT(24) /* non-secure */
 #define SCIF2_MSTP310          BIT(10) /* SCIF2 */
+#define DVFS_MSTP926           BIT(26)
+#define HSUSB_MSTP704          BIT(4)  /* HSUSB */
 
 int board_early_init_f(void)
 {
        /* TMU0,1 */            /* which use ? */
        mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
-       /* SCIF2 */
-       mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
 
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+       /* DVFS for reset */
+       mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
+#endif
        return 0;
 }
 
@@ -65,28 +70,73 @@ int board_early_init_f(void)
 /* -/W 32 Power resume control register 2 (3DG) */
 #define        SYSC_PWRONCR2   0xE618010C
 
+/* HSUSB block registers */
+#define HSUSB_REG_LPSTS                        0xE6590102
+#define HSUSB_REG_LPSTS_SUSPM_NORMAL   BIT(14)
+#define HSUSB_REG_UGCTRL2              0xE6590184
+#define HSUSB_REG_UGCTRL2_USB0SEL      0x30
+#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
+
 int board_init(void)
 {
        /* adress of boot parameters */
        gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
 
-       /* Init PFC controller */
-       r8a7795_pinmux_init();
-
+#if defined(CONFIG_R8A7795)
        /* GSX: force power and clock supply */
        writel(0x0000001F, SYSC_PWRONCR2);
        while (readl(SYSC_PWRSR2) != 0x000003E0)
                mdelay(20);
 
        mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
+#endif
+
+       /* USB1 pull-up */
+       setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
+
+       /* Configure the HSUSB block */
+       mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
+       /* Choice USB0SEL */
+       clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
+                       HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
+       /* low power status */
+       setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
 
        return 0;
 }
 
 int dram_init(void)
 {
-       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+       gd->ram_size = PHYS_SDRAM_1_SIZE;
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+       gd->ram_size += PHYS_SDRAM_2_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+       gd->ram_size += PHYS_SDRAM_3_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 4)
+       gd->ram_size += PHYS_SDRAM_4_SIZE;
+#endif
+
+       return 0;
+}
 
+int dram_init_banksize(void)
+{
+       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+#if (CONFIG_NR_DRAM_BANKS >= 2)
+       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+       gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 3)
+       gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+       gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+#endif
+#if (CONFIG_NR_DRAM_BANKS >= 4)
+       gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+       gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+#endif
        return 0;
 }
 
@@ -102,18 +152,10 @@ const struct rmobile_sysinfo sysinfo = {
 
 void reset_cpu(ulong addr)
 {
+#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
+       i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
+#else
        /* only CA57 ? */
        writel(RST_CODE, RST_CA57RESCNT);
+#endif
 }
-
-static const struct sh_serial_platdata serial_platdata = {
-       .base = SCIF2_BASE,
-       .type = PORT_SCIF,
-       .clk = 14745600,                /* 0xE10000 */
-       .clk_mode = EXT_CLK,
-};
-
-U_BOOT_DEVICE(salvator_x_scif2) = {
-       .name = "serial_sh",
-       .platdata = &serial_platdata,
-};