Merge branch 'master' of git://git.denx.de/u-boot-blackfin

[oweals/u-boot.git] / board / raidsonic / ib62x0 / kwbimage.cfg

diff --git a/board/raidsonic/ib62x0/kwbimage.cfg b/board/raidsonic/ib62x0/kwbimage.cfg
index 27a5e314afcafb7b5dee719c9256ac7a1a8f45a4..ec00c15af3d6e62bc84bcd44a2861b48063f2ee8 100644 (file)
--- a/board/raidsonic/ib62x0/kwbimage.cfg
+++ b/board/raidsonic/ib62x0/kwbimage.cfg
@@ -4,28 +4,14 @@
 # Simon Baatz <gmbnomis@gmail.com>
 # Luka Perkov <luka@openwrt.org>
 #
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see <http://www.gnu.org/licenses/>.
+# SPDX-License-Identifier:     GPL-2.0+
 #
 # Refer doc/README.kwbimage for more details about how-to configure
 # and create kirkwood boot image
 #
 
 # Boot Media configurations
-BOOT_FROM      nand    # change from nand to uart if building UART image
+BOOT_FROM      nand
 NAND_ECC_MODE  default
 NAND_PAGE_SIZE 0x0800
 
@@ -35,12 +21,12 @@ NAND_PAGE_SIZE      0x0800
 # Configure RGMII-0 interface pad voltage to 1.8V
 DATA 0xffd100e0 0x1b1b1b9b
 
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+# Dram initalization for SINGLE x16 CL=5 @ 400MHz
 DATA 0xffd01400 0x43000c30     # DDR Configuration register
 # bit13-0:  0xc30, (3120 DDR2 clks refresh rate)
 # bit23-14: 0x0,
-# bit24:    0x1,     enable exit self refresh mode on DDR access
-# bit25:    0x1,     required
+# bit24:    0x1,   enable exit self refresh mode on DDR access
+# bit25:    0x1,   required
 # bit29-26: 0x0,
 # bit31-30: 0x1,
 
@@ -78,10 +64,10 @@ DATA 0xffd01410 0x0000000c  # DDR Address Control
 # bit3-2:   11,  Cs0size (1Gb)
 # bit5-4:   00,  Cs1width (x8)
 # bit7-6:   11,  Cs1size (1Gb)
-# bit9-8:   00,  Cs2width (nonexistent
-# bit11-10: 00,  Cs2size  (nonexistent
-# bit13-12: 00,  Cs3width (nonexistent
-# bit15-14: 00,  Cs3size  (nonexistent
+# bit9-8:   00,  Cs2width (nonexistent)
+# bit11-10: 00,  Cs2size (nonexistent)
+# bit13-12: 00,  Cs3width (nonexistent)
+# bit15-14: 00,  Cs3size (nonexistent)
 # bit16:    0,   Cs0AddrSel
 # bit17:    0,   Cs1AddrSel
 # bit18:    0,   Cs2AddrSel
@@ -102,7 +88,7 @@ DATA 0xffd0141c 0x00000c52   # DDR Mode
 # bit6-4:   0x4, CL=5
 # bit7:     0x0, TestMode=0 normal
 # bit8:     0x0, DLL reset=0 normal
-# bit11-9:  0x6, auto-precharge write recovery ????????????
+# bit11-9:  0x6, auto-precharge write recovery
 # bit12:    0x0, PD must be zero
 # bit31-13: 0x0, required
 
@@ -162,8 +148,8 @@ DATA 0xffd0149c 0x0000e803  # CPU ODT Control
 DATA 0xffd01480 0x00000001     # DDR Initialization Control
 # bit0: 0x1, enable DDR init upon this register write
 
-DATA 0xFFD20134 0x66666666      # L2 RAM Timing 0 Register
-DATA 0xFFD20138 0x66666666      # L2 RAM Timing 1 Register
+DATA 0xffd20134 0x66666666     # L2 RAM Timing 0 Register
+DATA 0xffd20138 0x66666666     # L2 RAM Timing 1 Register
 
 # End of Header extension
 DATA 0x0 0x0