#include <common.h>
#include <command.h>
+#include <netdev.h>
#include <asm/inca-ip.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
+#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/cacheops.h>
+#include <asm/reboot.h>
#include "sconsole.h"
-#define cache_unroll(base,op) \
- __asm__ __volatile__(" \
- .set noreorder; \
- .set mips3; \
- cache %1, (%0); \
- .set mips0; \
- .set reorder" \
- : \
- : "r" (base), \
+#define cache_unroll(base,op) \
+ __asm__ __volatile__(" \
+ .set noreorder; \
+ .set mips3; \
+ cache %1, (%0); \
+ .set mips0; \
+ .set reorder" \
+ : \
+ : "r" (base), \
"i" (op));
typedef void (*FUNCPTR)(ulong *source, ulong *destination, ulong nlongs);
extern void asc_serial_init (void);
-extern void asc_serial_putc (char);
-extern void asc_serial_puts (const char *);
-extern int asc_serial_getc (void);
-extern int asc_serial_tstc (void);
-extern void asc_serial_setbrg (void);
+extern void asc_serial_putc (char);
+extern void asc_serial_puts (const char *);
+extern int asc_serial_getc (void);
+extern int asc_serial_tstc (void);
+extern void asc_serial_setbrg (void);
+void _machine_restart(void)
+{
+ void (*f)(void) = (void *) 0xbfc00000;
+
+ f();
+}
+
+static void sdram_timing_init (ulong size)
+{
+ register uint pass;
+ register uint done;
+ register uint count;
+ register uint p0, p1, p2, p3, p4;
+ register uint addr;
+
+#define WRITE_MC_IOGP_1 *(uint *)0xbf800800 = (p1<<14)+(p2<<13)+(p4<<8)+(p0<<4)+p3;
+#define WRITE_MC_IOGP_2 *(uint *)0xbf800800 = (p1<<14)+(p2<<13)+((p4-16)<<8)+(p0<<4)+p3;
+
+ done = 0;
+ p0 = 2;
+ while (p0 < 4 && done == 0) {
+ p1 = 0;
+ while (p1 < 2 && done == 0) {
+ p2 = 0;
+ while (p2 < 2 && done == 0) {
+ p3 = 0;
+ while (p3 < 16 && done == 0) {
+ count = 0;
+ p4 = 0;
+ while (p4 < 32 && done == 0) {
+ WRITE_MC_IOGP_1;
+
+ for (addr = CKSEG1 + 0x4000;
+ addr < CKSEG1ADDR (size);
+ addr = addr + 4) {
+ *(uint *) addr = 0xaa55aa55;
+ }
+
+ pass = 1;
+
+ for (addr = CKSEG1 + 0x4000;
+ addr < CKSEG1ADDR (size) && pass == 1;
+ addr = addr + 4) {
+ if (*(uint *) addr != 0xaa55aa55)
+ pass = 0;
+ }
+
+ if (pass == 1) {
+ count++;
+ } else {
+ count = 0;
+ }
+
+ if (count == 32) {
+ WRITE_MC_IOGP_2;
+ done = 1;
+ }
+ p4++;
+ }
+ p3++;
+ }
+ p2++;
+ }
+ p1++;
+ }
+ p0++;
+ if (p0 == 1)
+ p0++;
+ }
+}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
/* The only supported number of SDRAM banks is 4.
*/
-#define CFG_NB 4
+#define CONFIG_SYS_NB 4
ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0;
ulong cfgdw = *INCA_IP_SDRAM_MC_CFGDW;
int cols = cfgpb0 & 0xF;
int rows = (cfgpb0 & 0xF0) >> 4;
int dw = cfgdw & 0xF;
- ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB;
+ ulong size = (1 << (rows + cols)) * (1 << (dw - 1)) * CONFIG_SYS_NB;
+ void (* sdram_init) (ulong);
+
+ sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init);
+
+ sdram_init(0x10000);
return size;
}
printf("CPU Speed %d MHz\n", CPU_CLOCK_RATE/1000000);
+ set_io_port_base(0);
+
return 0;
}
ulong temp,temp1;
ulong *dstend = destination + nlongs;
- while (destination < dstend)
- {
+ while (destination < dstend) {
temp = *source++;
/* dummy read from sdram */
temp1 = *(ulong *)0xa0000000;
*(ulong *)0xbf0081f8 = temp1 + temp;
*destination++ = temp;
- }
+ }
}
/*******************************************************************************
src = (ulong *)(TEXT_BASE + 0x428);
dst = (ulong *)0xbf0081d0;
- absEntry = (FUNCPTR)(TEXT_BASE + 0x400);
- absEntry(src,dst,0x6);
+ absEntry = (FUNCPTR)(TEXT_BASE + 0x400);
+ absEntry(src,dst,0x6);
src = (ulong *)((ulong)copydwords & 0xfffffff8);
dst = (ulong *)0xbf008000;
*/
void copy_code (ulong dest_addr)
{
+ extern long uboot_end_data;
unsigned long start;
unsigned long end;
/* copy u-boot code
*/
- copyLongs((ulong *)CFG_MONITOR_BASE,
+ copyLongs((ulong *)CONFIG_SYS_MONITOR_BASE,
(ulong *)dest_addr,
- (CFG_MONITOR_LEN + 3) / 4);
+ ((ulong)&uboot_end_data - CONFIG_SYS_MONITOR_BASE + 3) / 4);
/* flush caches
*/
- start = KSEG0;
- end = start + CFG_DCACHE_SIZE;
+ start = CKSEG0;
+ end = start + CONFIG_SYS_DCACHE_SIZE;
while(start < end) {
cache_unroll(start,Index_Writeback_Inv_D);
- start += CFG_CACHELINE_SIZE;
+ start += CONFIG_SYS_CACHELINE_SIZE;
}
- start = KSEG0;
- end = start + CFG_ICACHE_SIZE;
+ start = CKSEG0;
+ end = start + CONFIG_SYS_ICACHE_SIZE;
while(start < end) {
cache_unroll(start,Index_Invalidate_I);
- start += CFG_CACHELINE_SIZE;
+ start += CONFIG_SYS_CACHELINE_SIZE;
}
}
+
+#ifdef CONFIG_PLB2800_ETHER
+int board_eth_init(bd_t *bis)
+{
+ return plb2800_eth_initialize(bis);
+}
+#endif