#include <common.h>
#include <netdev.h>
#include <twl4030.h>
+#include <linux/mtd/nand.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/omap_gpmc.h>
#include <asm/gpio.h>
#include <asm/mach-types.h>
#include "overo.h"
{
int revision;
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+ unsigned char data;
+
+ /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */
+ /* these boards should return a revision number of 0 */
+ /* the code below forces a 4030 RTC irq to ensure that gpio112 is low */
+ i2c_set_bus_num(TWL4030_I2C_BUS);
+ data = 0x01;
+ i2c_write(0x4B, 0x29, 1, &data, 1);
+ data = 0x0c;
+ i2c_write(0x4B, 0x2b, 1, &data, 1);
+ i2c_read(0x4B, 0x2a, 1, &data, 1);
+#endif
+
if (!gpio_request(112, "") &&
!gpio_request(113, "") &&
!gpio_request(115, "")) {
revision = gpio_get_value(115) << 2 |
gpio_get_value(113) << 1 |
gpio_get_value(112);
-
- gpio_free(112);
- gpio_free(113);
- gpio_free(115);
} else {
- printf("Error: unable to acquire board revision GPIOs\n");
+ puts("Error: unable to acquire board revision GPIOs\n");
revision = -1;
}
return revision;
}
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ timings->mr = MICRON_V_MR_165;
+ switch (get_board_revision()) {
+ case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ break;
+ case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
+ timings->mcfg = MICRON_V_MCFG_165(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ break;
+ case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
+ timings->mcfg = HYNIX_V_MCFG_165(256 << 20);
+ timings->ctrla = HYNIX_V_ACTIMA_165;
+ timings->ctrlb = HYNIX_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ break;
+ default:
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ }
+}
+#endif
+
/*
* Routine: get_sdio2_config
* Description: Return information about the wifi module connection
sdio_direct = 0;
}
- gpio_free(130);
- gpio_free(139);
+ gpio_direction_input(130);
} else {
- printf("Error: unable to acquire sdio2 clk GPIOs\n");
+ puts("Error: unable to acquire sdio2 clk GPIOs\n");
sdio_direct = -1;
}
switch (get_sdio2_config()) {
case 0:
- printf("Tranceiver detected on mmc2\n");
+ puts("Tranceiver detected on mmc2\n");
MUX_OVERO_SDIO2_TRANSCEIVER();
break;
case 1:
- printf("Direct connection on mmc2\n");
+ puts("Direct connection on mmc2\n");
MUX_OVERO_SDIO2_DIRECT();
break;
default:
- printf("Unable to detect mmc2 connection type\n");
+ puts("Unable to detect mmc2 connection type\n");
}
switch (get_expansion_id()) {
printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
+ /* second lan chip */
+ enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4],
+ 0x2B000000, GPMC_SIZE_16M);
break;
case GUMSTIX_PALO35:
printf("Recognized Palo35 expansion board (rev %d %s)\n",
setenv("defaultdisplay", "dvi");
break;
case GUMSTIX_NO_EEPROM:
- printf("No EEPROM on expansion board\n");
+ puts("No EEPROM on expansion board\n");
break;
default:
- printf("Unrecognized expansion board\n");
+ puts("Unrecognized expansion board\n");
}
if (expansion_config.content == 1)
enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
GPMC_SIZE_16M);
- /* second lan chip */
- enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], 0x2B000000,
- GPMC_SIZE_16M);
-
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
return rc;
}
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0);
+ omap_mmc_init(0, 0, 0);
return 0;
}
#endif