Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

[oweals/u-boot.git] / board / overo / overo.c

diff --git a/board/overo/overo.c b/board/overo/overo.c
index 4a20c7fec3df93ee9ed075dc1d0ae0b6e994883a..fdf46a2aae92101bc2957eab45144f3a6c6571eb 100644 (file)
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -31,6 +31,7 @@
 #include <common.h>
 #include <netdev.h>
 #include <twl4030.h>
+#include <linux/mtd/nand.h>
 #include <asm/io.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/mux.h>
@@ -107,6 +108,20 @@ int get_board_revision(void)
 {
        int revision;
 
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+       unsigned char data;
+
+       /* board revisions <= R2410 connect 4030 irq_1 to gpio112             */
+       /* these boards should return a revision number of 0                  */
+       /* the code below forces a 4030 RTC irq to ensure that gpio112 is low */
+       i2c_set_bus_num(TWL4030_I2C_BUS);
+       data = 0x01;
+       i2c_write(0x4B, 0x29, 1, &data, 1);
+       data = 0x0c;
+       i2c_write(0x4B, 0x2b, 1, &data, 1);
+       i2c_read(0x4B, 0x2a, 1, &data, 1);
+#endif
+
        if (!gpio_request(112, "") &&
            !gpio_request(113, "") &&
            !gpio_request(115, "")) {
@@ -126,6 +141,43 @@ int get_board_revision(void)
        return revision;
 }
 
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+       timings->mr = MICRON_V_MR_165;
+       switch (get_board_revision()) {
+       case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
+               timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+               timings->ctrla = MICRON_V_ACTIMA_165;
+               timings->ctrlb = MICRON_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               break;
+       case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
+               timings->mcfg = MICRON_V_MCFG_165(256 << 20);
+               timings->ctrla = MICRON_V_ACTIMA_165;
+               timings->ctrlb = MICRON_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               break;
+       case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
+               timings->mcfg = HYNIX_V_MCFG_165(256 << 20);
+               timings->ctrla = HYNIX_V_ACTIMA_165;
+               timings->ctrlb = HYNIX_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               break;
+       default:
+               timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+               timings->ctrla = MICRON_V_ACTIMA_165;
+               timings->ctrlb = MICRON_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+       }
+}
+#endif
+
 /*
  * Routine: get_sdio2_config
  * Description: Return information about the wifi module connection
@@ -337,10 +389,10 @@ int board_eth_init(bd_t *bis)
        return rc;
 }
 
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
-       omap_mmc_init(0);
+       omap_mmc_init(0, 0, 0);
        return 0;
 }
 #endif