omap: overo: Use 200MHz SDRC timings for revision 1, 2 & 3 boards

[oweals/u-boot.git] / board / overo / overo.c

diff --git a/board/overo/overo.c b/board/overo/overo.c
index 92d3de450eca9f060b57358e5d7bafe5ae24c88c..aace42a8be504446b5cd44d93397f5413c5231dc 100644 (file)
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -142,16 +142,16 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
                timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                break;
        case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
-               timings->mcfg = MICRON_V_MCFG_165(256 << 20);
-               timings->ctrla = MICRON_V_ACTIMA_165;
-               timings->ctrlb = MICRON_V_ACTIMB_165;
-               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+               timings->ctrla = MICRON_V_ACTIMA_200;
+               timings->ctrlb = MICRON_V_ACTIMB_200;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
                break;
        case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
-               timings->mcfg = HYNIX_V_MCFG_165(256 << 20);
-               timings->ctrla = HYNIX_V_ACTIMA_165;
-               timings->ctrlb = HYNIX_V_ACTIMB_165;
-               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+               timings->ctrla = HYNIX_V_ACTIMA_200;
+               timings->ctrlb = HYNIX_V_ACTIMB_200;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
                break;
        case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */
                timings->mcfg = MCFG(512 << 20, 15);