ppc4xx: lwmon5: Change PHY reset sequence for PHY MDIO address latching

[oweals/u-boot.git] / board / nc650 / nc650.c

diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c
index 376dbbdca32d304061bfa6f15a216bf5a9337b04..707e4b97d1713099d258cc732dc22c4beeac0560 100644 (file)
--- a/board/nc650/nc650.c
+++ b/board/nc650/nc650.c
@@ -1,4 +1,5 @@
 /*
+ * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
  * (C) Copyright 2001
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
@@ -70,6 +71,36 @@ const uint sdram_table[] = {
        0x7ffffc07, _not_used_, _not_used_, _not_used_
 };
 
+const uint nand_flash_table[] = {
+       /* single read. (offset 0 in upm RAM) */
+       0x0ff3fc04, 0x0ff3fc04, 0x0ff3fc04, 0x0ffffc04,
+       0xfffffc00, 0xfffffc05, 0xfffffc05, 0xfffffc05,
+
+       /* burst read. (offset 8 in upm RAM) */
+       0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+       0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+       0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+       0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+
+       /* single write. (offset 18 in upm RAM) */
+       0x00fffc04, 0x00fffc04, 0x00fffc04, 0x0ffffc04,
+       0x0ffffc84, 0x0ffffc84, 0xfffffc00, 0xfffffc05,
+
+       /* burst write. (offset 20 in upm RAM) */
+       0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+       0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+       0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+       0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+
+       /* refresh. (offset 30 in upm RAM) */
+       0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+       0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+       0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
+
+       /* exception. (offset 3c in upm RAM) */
+       0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05
+};
+
 /* ------------------------------------------------------------------------- */
 
 /*
@@ -78,7 +109,16 @@ const uint sdram_table[] = {
 
 int checkboard (void)
 {
-       puts ("Board: NC650\n");
+#if !defined(CONFIG_CP850)
+       puts ("Board: NC650");
+#else
+       puts ("Board: CP850");
+#endif
+#if defined(CONFIG_IDS852_REV1)
+       puts (" with IDS852 rev 1 module\n");
+#elif defined(CONFIG_IDS852_REV2)
+       puts (" with IDS852 rev 2 module\n");
+#endif
        return 0;
 }
 
@@ -137,16 +177,14 @@ long int initdram (int board_type)
         *
         * try 8 column mode
         */
-       size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
-                                          SDRAM_MAX_SIZE);
+       size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
 
        udelay (1000);
 
        /*
         * try 9 column mode
         */
-       size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE3_PRELIM,
-                                         SDRAM_MAX_SIZE);
+       size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
 
        udelay (1000);
 
@@ -182,6 +220,12 @@ long int initdram (int board_type)
 
        udelay (10000);
 
+       /* Configure UPMB for NAND flash access */
+       upmconfig (UPMB, (uint *) nand_flash_table,
+                          sizeof (nand_flash_table) / sizeof (uint));
+
+       memctl->memc_mbmr = CFG_MBMR_NAND;
+
        return (size_b0);
 }
 
@@ -195,8 +239,7 @@ long int initdram (int board_type)
  * - short between data lines
  */
 
-static long int dram_size (long int mamr_value, long int *base,
-                                                  long int maxsize)
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
 {
        volatile immap_t *immap = (immap_t *) CFG_IMMR;
        volatile memctl8xx_t *memctl = &immap->im_memctl;
@@ -205,3 +248,62 @@ static long int dram_size (long int mamr_value, long int *base,
 
        return (get_ram_size(base, maxsize));
 }
+
+
+#if defined(CONFIG_CP850)
+
+#define DPRAM_VARNAME           "KP850DIP"
+#define PARAM_ADDR              0x7C0
+#define NAME_ADDR               0x7F8
+#define BOARD_NAME              "KP01"
+#define DEFAULT_LB              "241111"
+
+int misc_init_r(void)
+{
+       int             iCompatMode = 0;
+       char            *pParam = NULL;
+       char            *envlb;
+
+       /*
+          First byte in CPLD read address space signals compatibility mode
+          0 - cp850
+          1 - kp852
+       */
+       pParam = (char*)(CFG_CPLD_BASE);
+       if( *pParam != 0)
+               iCompatMode = 1;
+
+       if ( iCompatMode != 0) {
+               /*
+                  In KP852 compatibility mode we have to write to
+                  DPRAM as early as possible the binary coded
+                  line config and board name.
+                  The line config is derived from the environment
+                  variable DPRAM_VARNAME by converting from ASCII
+                  to binary per character.
+               */
+               if ( (envlb = getenv ( DPRAM_VARNAME )) == 0) {
+                       setenv( DPRAM_VARNAME, DEFAULT_LB);
+                       envlb = DEFAULT_LB;
+               }
+
+               /* Status string */
+               printf("Mode:  KP852(LB=%s)\n", envlb);
+
+               /* copy appl init */
+               pParam = (char*)(DPRAM_BASE_ADDR + PARAM_ADDR);
+               while (*envlb) {
+                       *(pParam++) = *(envlb++) - '0';
+               }
+               *pParam = '\0';
+
+               /* copy board id */
+               pParam = (char*)(DPRAM_BASE_ADDR + NAME_ADDR);
+               strcpy( pParam, BOARD_NAME);
+       } else {
+               puts("Mode:  CP850\n");
+       }
+
+       return 0;
+}
+#endif