MPC512x: add more hardware description to immap_512x.h

[oweals/u-boot.git] / board / nc650 / nc650.c

diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c
index fe96b93816f5932068b4fcb6412deefbdd574569..056230da61cc360e24f7dc5c75e0b6f461081618 100644 (file)
--- a/board/nc650/nc650.c
+++ b/board/nc650/nc650.c
@@ -1,4 +1,5 @@
 /*
+ * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
  * (C) Copyright 2001
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
@@ -108,7 +109,16 @@ const uint nand_flash_table[] = {
 
 int checkboard (void)
 {
-       puts ("Board: NC650\n");
+#if !defined(CONFIG_CP850)
+       puts ("Board: NC650");
+#else
+       puts ("Board: CP850");
+#endif
+#if defined(CONFIG_IDS852_REV1)
+       puts (" with IDS852 rev 1 module\n");
+#elif defined(CONFIG_IDS852_REV2)
+       puts (" with IDS852 rev 2 module\n");
+#endif
        return 0;
 }
 
@@ -118,9 +128,9 @@ static long int dram_size (long int, long int *, long int);
 
 /* ------------------------------------------------------------------------- */
 
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
-       volatile immap_t *immap = (immap_t *) CFG_IMMR;
+       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
        volatile memctl8xx_t *memctl = &immap->im_memctl;
        long int size8, size9;
        long int size_b0 = 0;
@@ -135,7 +145,7 @@ long int initdram (int board_type)
         * with two SDRAM banks or four cycles every 31.2 us with one
         * bank. It will be adjusted after memory sizing.
         */
-       memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+       memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 
        memctl->memc_mar = 0x00000088;
 
@@ -144,10 +154,10 @@ long int initdram (int board_type)
         * preliminary address - these have to be modified after the
         * SDRAM size has been determined.
         */
-       memctl->memc_or3 = CFG_OR3_PRELIM;
-       memctl->memc_br3 = CFG_BR3_PRELIM;
+       memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+       memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 
-       memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));     /* no refresh yet */
+       memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));      /* no refresh yet */
 
        udelay (200);
 
@@ -167,16 +177,14 @@ long int initdram (int board_type)
         *
         * try 8 column mode
         */
-       size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
-                                          SDRAM_MAX_SIZE);
+       size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
 
        udelay (1000);
 
        /*
         * try 9 column mode
         */
-       size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE3_PRELIM,
-                                         SDRAM_MAX_SIZE);
+       size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
 
        udelay (1000);
 
@@ -184,7 +192,7 @@ long int initdram (int board_type)
                size_b0 = size9;
        } else {
                size_b0 = size8;
-               memctl->memc_mamr = CFG_MAMR_8COL;
+               memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
                udelay (500);
        }
 
@@ -194,7 +202,7 @@ long int initdram (int board_type)
         */
        if ((size_b0 < 0x02000000)) {
                /* reduce to 15.6 us (62.4 us / quad) */
-               memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+               memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
                udelay (1000);
        }
 
@@ -202,12 +210,12 @@ long int initdram (int board_type)
         * Final mapping
         */
 
-       memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-       memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+       memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+       memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
        /* adjust refresh rate depending on SDRAM type, one bank */
        reg = memctl->memc_mptpr;
-       reg >>= 1;                                      /* reduce to CFG_MPTPR_1BK_8K / _4K */
+       reg >>= 1;                                      /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
        memctl->memc_mptpr = reg;
 
        udelay (10000);
@@ -216,7 +224,7 @@ long int initdram (int board_type)
        upmconfig (UPMB, (uint *) nand_flash_table,
                           sizeof (nand_flash_table) / sizeof (uint));
 
-       memctl->memc_mbmr = CFG_MBMR_NAND;
+       memctl->memc_mbmr = CONFIG_SYS_MBMR_NAND;
 
        return (size_b0);
 }
@@ -233,7 +241,7 @@ long int initdram (int board_type)
 
 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
 {
-       volatile immap_t *immap = (immap_t *) CFG_IMMR;
+       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
        volatile memctl8xx_t *memctl = &immap->im_memctl;
 
        memctl->memc_mamr = mamr_value;
@@ -241,13 +249,61 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
        return (get_ram_size(base, maxsize));
 }
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-void nand_init(void)
+
+#if defined(CONFIG_CP850)
+
+#define DPRAM_VARNAME           "KP850DIP"
+#define PARAM_ADDR              0x7C0
+#define NAME_ADDR               0x7F8
+#define BOARD_NAME              "KP01"
+#define DEFAULT_LB              "241111"
+
+int misc_init_r(void)
 {
-       extern unsigned long nand_probe(unsigned long physadr);
+       int             iCompatMode = 0;
+       char            *pParam = NULL;
+       char            *envlb;
 
-       unsigned long totlen = nand_probe(CFG_NAND_BASE);
+       /*
+          First byte in CPLD read address space signals compatibility mode
+          0 - cp850
+          1 - kp852
+       */
+       pParam = (char*)(CONFIG_SYS_CPLD_BASE);
+       if( *pParam != 0)
+               iCompatMode = 1;
+
+       if ( iCompatMode != 0) {
+               /*
+                  In KP852 compatibility mode we have to write to
+                  DPRAM as early as possible the binary coded
+                  line config and board name.
+                  The line config is derived from the environment
+                  variable DPRAM_VARNAME by converting from ASCII
+                  to binary per character.
+               */
+               if ( (envlb = getenv ( DPRAM_VARNAME )) == 0) {
+                       setenv( DPRAM_VARNAME, DEFAULT_LB);
+                       envlb = DEFAULT_LB;
+               }
+
+               /* Status string */
+               printf("Mode:  KP852(LB=%s)\n", envlb);
+
+               /* copy appl init */
+               pParam = (char*)(DPRAM_BASE_ADDR + PARAM_ADDR);
+               while (*envlb) {
+                       *(pParam++) = *(envlb++) - '0';
+               }
+               *pParam = '\0';
+
+               /* copy board id */
+               pParam = (char*)(DPRAM_BASE_ADDR + NAME_ADDR);
+               strcpy( pParam, BOARD_NAME);
+       } else {
+               puts("Mode:  CP850\n");
+       }
 
-       printf ("%4lu MB\n", totlen >> 20);
+       return 0;
 }
 #endif