Merge branch 'master' of git://git.denx.de/u-boot-blackfin

[oweals/u-boot.git] / board / mpl / pip405 / pip405.c

diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
index a398362f96aef4fad6eab5f3f77e22681ba831f0..677437d09ea99526698509403cddf7b54c439524 100644 (file)
--- a/board/mpl/pip405/pip405.c
+++ b/board/mpl/pip405/pip405.c
@@ -28,9 +28,12 @@
 #include "pip405.h"
 #include <asm/processor.h>
 #include <i2c.h>
+#include <stdio_dev.h>
 #include "../common/isa.h"
 #include "../common/common_util.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #undef SDRAM_DEBUG
 
 #define FALSE           0
@@ -134,8 +137,6 @@ unsigned short NSto10PS (unsigned char spd_byte)
 void SDRAM_err (const char *s)
 {
 #ifndef SDRAM_DEBUG
-       DECLARE_GLOBAL_DATA_PTR;
-
        (void) get_clocks ();
        gd->baudrate = 9600;
        serial_init ();
@@ -191,9 +192,6 @@ int board_early_init_f (void)
                        trc_clocks, tctp_clocks;
        unsigned char cal_index, cal_val, spd_version, spd_chksum;
        unsigned char buf[8];
-#ifdef SDRAM_DEBUG
-       DECLARE_GLOBAL_DATA_PTR;
-#endif
        /* set up the config port */
        mtdcr (ebccfga, pb7ap);
        mtdcr (ebccfgd, CONFIG_PORT_AP);
@@ -211,7 +209,7 @@ int board_early_init_f (void)
 #endif
 
        /* Read Serial Presence Detect Information */
-       i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+       i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
        dataout[0] = 0;
        for (i = 0; i < 128; i++)
                datain[i] = 127;
@@ -255,7 +253,7 @@ int board_early_init_f (void)
                (datain[2] != 0x04) ||  /* if not SDRAM */
                (!((datain[6] == 0x40) || (datain[6] == 0x48))) ||      /* or not (64 Bit or 72 Bit)  */
                (datain[7] != 0x00) || (datain[8] != 0x01) ||   /* or not LVTTL signal levels */
-               (datain[126] == 0x66))  /* or a 66Mhz modules */
+               (datain[126] == 0x66))  /* or a 66MHz modules */
                SDRAM_err ("unsupported SDRAM");
 #ifdef SDRAM_DEBUG
        serial_puts ("SDRAM sanity ok\n");
@@ -389,7 +387,7 @@ int board_early_init_f (void)
        /* write SDRAM timing register */
        mtdcr (memcfga, mem_sdtr1);
        mtdcr (memcfgd, tmp);
-       baseaddr = CFG_SDRAM_BASE;
+       baseaddr = CONFIG_SYS_SDRAM_BASE;
        bank_size = (((unsigned long) density) << 22) / 2;
        /* insert AM value */
        tmp = ((unsigned long) t->mode - 1) << 13;
@@ -611,10 +609,8 @@ int checkboard (void)
 /* ------------------------------------------------------------------------- */
 static int test_dram (unsigned long ramsize);
 
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        unsigned long bank_reg[4], tmp, bank_size;
        int i, ds;
        unsigned long TotalSize;
@@ -666,15 +662,14 @@ extern flash_info_t flash_info[]; /* info for FLASH chips */
 
 int misc_init_r (void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
        /* adjust flash start and size as well as the offset */
        gd->bd->bi_flashstart=0-flash_info[0].size;
-       gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
+       gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
        gd->bd->bi_flashoffset=0;
 
        /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
        if (mfdcr(strap) & PSR_ROM_LOC)
-              mtspr(ccr0, (mfspr(ccr0) & ~0x80));
+              mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
 
        return (0);
 }
@@ -711,7 +706,7 @@ int last_stage_init (void)
 {
        print_pip405_rev ();
        isa_init ();
-       show_stdio_dev ();
+       stdio_print_current_devices ();
        check_env();
        return 0;
 }