* PSDMR_BUFCMD adds a clock
* 0 no extra clock
*/
-#define CONFIG_PBI PSDMR_PBI
+#define CONFIG_PBI 0
#define PESSIMISTIC_SDRAM 0
#define EAMUX 0 /* EST requires EAMUX */
#define BUFCMD 0
}
-int board_pre_init (void)
+int board_early_init_f (void)
{
volatile bcsr_t *bcsr = (bcsr_t *)CFG_BCSR;
volatile pci_ic_t *pci_ic = (pci_ic_t *) CFG_PCI_INT;
bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
sda10 = sdam + 2;
#else
- sdam = cols - 6;
+ sdam = cols + banks - 8;
bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
sda10 = sdam;
#endif
printf("SDRAM configuration read from SPD\n");
printf("\tSize per side = %dMB\n", sdram_size >> 20);
printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width);
- printf("\tRefresh rate = %d, CAS latency = %d\n", psrt, caslatency);
+ printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency);
+#if(CONFIG_PBI == 0) /* bank-based interleaving */
+ printf(", Using Bank Based Interleave\n");
+#else
+ printf(", Using Page Based Interleave\n");
+#endif
printf("\tTotal size: ");
+ /* this delay only needed for original 16MB DIMM...
+ * Not needed for any other memory configuration */
+ if ((sdram_size * chipselects) == (16 *1024 *1024))
+ udelay (250000);
return (sdram_size * chipselects);
/*return (16 * 1024 * 1024);*/
}