#include <mpc5xxx.h>
#include <pci.h>
-#include "mt48lc8m32b2-6-7.h"
+/* Two MT48LC8M32B2 for 32 MB */
+/* #include "mt48lc8m32b2-6-7.h" */
+
+/* One MT48LC16M32S2 for 64 MB */
+#include "mt48lc16m32s2-75.h"
DECLARE_GLOBAL_DATA_PTR;
/* normal operation */
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
__asm__ volatile ("sync");
+
+ udelay(10);
}
#endif
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
}
+ if (gd->bd->bi_flashsize > (32 << 20)) {
+ /* Unprotect the upper bank of the Flash */
+ *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
+ flash_protect (FLAG_PROTECT_CLEAR,
+ flash_info[0].start[0] + flash_info[0].size / 2,
+ (flash_info[0].start[0] + flash_info[0].size) / 2 - 1,
+ &flash_info[0]);
+ *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
+ }
+
return (0);
}