Merge branch '2020-05-18-reduce-size-of-common.h'

[oweals/u-boot.git] / board / keymile / km_arm / fpga_config.c

diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c
index cbfc7d21759031668e07629a982f7e3809fea3ad..abb5b7d60d0e1d3397a314a287bef687b2a35f00 100644 (file)
--- a/board/keymile/km_arm/fpga_config.c
+++ b/board/keymile/km_arm/fpga_config.c
@@ -1,13 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2012
  * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <i2c.h>
-#include <asm/errno.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
 
 /* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
 #define KM_XLX_PROGRAM_B_PIN    39
@@ -83,6 +83,7 @@ static int boco_set_bits(u8 reg, u8 flags)
 #define FPGA_INIT_B    0x10
 #define FPGA_DONE      0x20
 
+#ifndef CONFIG_KM_FPGA_FORCE_CONFIG
 static int fpga_done(void)
 {
        int ret = 0;
@@ -101,13 +102,16 @@ static int fpga_done(void)
 
        return regval & FPGA_DONE ? 1 : 0;
 }
+#endif /* CONFIG_KM_FPGA_FORCE_CONFIG */
 
-int skip;
+static int skip;
 
 int trigger_fpga_config(void)
 {
        int ret = 0;
 
+       skip = 0;
+#ifndef CONFIG_KM_FPGA_FORCE_CONFIG
        /* if the FPGA is already configured, we do not want to
         * reconfigure it */
        skip = 0;
@@ -116,6 +120,7 @@ int trigger_fpga_config(void)
                skip = 1;
                return 0;
        }
+#endif /* CONFIG_KM_FPGA_FORCE_CONFIG */
 
        if (check_boco2()) {
                /* we have a BOCO2, this has to be triggered here */
@@ -189,6 +194,14 @@ int wait_for_fpga_config(void)
        return 0;
 }
 
+#if defined(CONFIG_KM_FPGA_NO_RESET)
+int fpga_reset(void)
+{
+       /* no dedicated reset pin for FPGA */
+       return 0;
+}
+#else
+
 #define PRST1          0x4
 #define PCIE_RST       0x10
 #define TRAFFIC_RST    0x04
@@ -219,6 +232,7 @@ int fpga_reset(void)
 
        return 0;
 }
+#endif
 
 /* the FPGA was configured, we configure the BOCO2 so that the EEPROM
  * is available from the Bobcat SPI bus */