* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
/* ------------------------------------------------------------------------- */
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
long int size_b0;
/* enable SDRAM clock ("switch on" SDRAM) */
- immr->im_cpm.cp_pbpar &= ~(CFG_PB_SDRAM_CLKE); /* GPIO */
- immr->im_cpm.cp_pbodr &= ~(CFG_PB_SDRAM_CLKE); /* active output */
- immr->im_cpm.cp_pbdir |= CFG_PB_SDRAM_CLKE; /* output */
- immr->im_cpm.cp_pbdat |= CFG_PB_SDRAM_CLKE; /* assert SDRAM CLKE */
+ immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_SDRAM_CLKE); /* GPIO */
+ immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_SDRAM_CLKE); /* active output */
+ immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_SDRAM_CLKE; /* output */
+ immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_SDRAM_CLKE; /* assert SDRAM CLKE */
udelay (1);
/*
* Map controller bank 1 for ELIC SACCO
*/
- memctl->memc_or1 = CFG_OR1;
- memctl->memc_br1 = CFG_BR1;
+ memctl->memc_or1 = CONFIG_SYS_OR1;
+ memctl->memc_br1 = CONFIG_SYS_BR1;
/*
* Map controller bank 2 for ELIC EPIC
*/
- memctl->memc_or2 = CFG_OR2;
- memctl->memc_br2 = CFG_BR2;
+ memctl->memc_or2 = CONFIG_SYS_OR2;
+ memctl->memc_br2 = CONFIG_SYS_BR2;
/*
* Configure UPMA for SHARC
/*
* Map controller bank 4 for HDLC Address space
*/
- memctl->memc_or4 = CFG_OR4;
- memctl->memc_br4 = CFG_BR4;
+ memctl->memc_or4 = CONFIG_SYS_OR4;
+ memctl->memc_br4 = CONFIG_SYS_BR4;
#endif
/*
* Map controller bank 5 for SHARC
*/
- memctl->memc_or5 = CFG_OR5;
- memctl->memc_br5 = CFG_BR5;
+ memctl->memc_or5 = CONFIG_SYS_OR5;
+ memctl->memc_br5 = CONFIG_SYS_BR5;
memctl->memc_mamr = 0x00001000;
upmconfig (UPMB, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
- memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
memctl->memc_mar = 0x00000088;
/*
* Map controller bank 3 to the SDRAM bank at preliminary address.
*/
- memctl->memc_or3 = CFG_OR3_PRELIM;
- memctl->memc_br3 = CFG_BR3_PRELIM;
+ memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+ memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
- memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
+ memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */
udelay (200);
memctl->memc_mcr = 0x80806105; /* precharge */
* Check Bank 0 Memory Size for re-configuration
*/
size_b0 =
- dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM,
+ dram_size (CONFIG_SYS_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
- memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
+ memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;
return (size_b0);
}
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
memctl->memc_mbmr = mamr_value;
void reset_phy (void)
{
- immap_t *immr = (immap_t *) CFG_IMMR;
+ immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
/* De-assert Ethernet Powerdown */
- immr->im_cpm.cp_pbpar &= ~(CFG_PB_ETH_POWERDOWN); /* GPIO */
- immr->im_cpm.cp_pbodr &= ~(CFG_PB_ETH_POWERDOWN); /* active output */
- immr->im_cpm.cp_pbdir |= CFG_PB_ETH_POWERDOWN; /* output */
- immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
+ immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* GPIO */
+ immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* active output */
+ immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_ETH_POWERDOWN; /* output */
+ immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */
udelay (1000);
/*
* Note: The RESET pin is high active, but there is an
* inverter on the SPD823TS board...
*/
- immr->im_ioport.iop_pcpar &= ~(CFG_PC_ETH_RESET);
- immr->im_ioport.iop_pcdir |= CFG_PC_ETH_RESET;
+ immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_ETH_RESET);
+ immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_ETH_RESET;
/* assert RESET signal of PHY */
- immr->im_ioport.iop_pcdat &= ~(CFG_PC_ETH_RESET);
+ immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_ETH_RESET);
udelay (10);
/* de-assert RESET signal of PHY */
- immr->im_ioport.iop_pcdat |= CFG_PC_ETH_RESET;
+ immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_ETH_RESET;
udelay (10);
}
(status < 0) ? STATUS_LED_ON : STATUS_LED_OFF);
# endif /* STATUS_LED_YELLOW */
# if defined(STATUS_LED_BOOT)
- if (status == 6)
+ if (status == BOOTSTAGE_ID_DECOMP_IMAGE)
status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF);
# endif /* STATUS_LED_BOOT */
#endif /* CONFIG_STATUS_LED */
void ide_set_reset (int on)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ int i;
/*
* Configure PC for IDE Reset Pin
*/
if (on) { /* assert RESET */
- immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
+ immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
+
+#ifdef CONFIG_SYS_PB_12V_ENABLE
+ /* 12V Enable output OFF */
+ immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_12V_ENABLE);
+
+ immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_12V_ENABLE);
+ immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_12V_ENABLE);
+ immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_12V_ENABLE;
+
+ /* wait 500 ms for the voltage to stabilize */
+ for (i = 0; i < 500; ++i)
+ udelay(1000);
+#endif /* CONFIG_SYS_PB_12V_ENABLE */
} else { /* release RESET */
- immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
+#ifdef CONFIG_SYS_PB_12V_ENABLE
+ /* 12V Enable output ON */
+ immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_12V_ENABLE;
+#endif /* CONFIG_SYS_PB_12V_ENABLE */
+
+#ifdef CONFIG_SYS_PB_IDE_MOTOR
+ /* configure IDE Motor voltage monitor pin as input */
+ immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_IDE_MOTOR);
+ immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_IDE_MOTOR);
+ immr->im_cpm.cp_pbdir &= ~(CONFIG_SYS_PB_IDE_MOTOR);
+
+/* wait up to 1 s for the motor voltage to stabilize */
+ for (i = 0; i < 1000; ++i) {
+ if ((immr->im_cpm.cp_pbdat
+ & CONFIG_SYS_PB_IDE_MOTOR) != 0)
+ break;
+ udelay(1000);
+ }
+
+ if (i == 1000) { /* Timeout */
+ printf("\nWarning: 5V for IDE Motor missing\n");
+#ifdef CONFIG_STATUS_LED
+#ifdef STATUS_LED_YELLOW
+ status_led_set(STATUS_LED_YELLOW, STATUS_LED_ON);
+#endif
+#ifdef STATUS_LED_GREEN
+ status_led_set(STATUS_LED_GREEN, STATUS_LED_OFF);
+#endif
+#endif /* CONFIG_STATUS_LED */
+ }
+#endif /* CONFIG_SYS_PB_IDE_MOTOR */
+
+ immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
}
/* program port pin as GPIO output */
- immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
- immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
- immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
+ immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
+ immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET);
+ immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET;
}
/* ------------------------------------------------------------------------- */