Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging

[oweals/u-boot.git] / board / isee / igep0030 / igep0030.c

diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c
index bb4dc3ba1743ef87dccc48f893982e9a967c48f3..107cb7f8e0581d0f8c7c5487773e6873eec70cfe 100644 (file)
--- a/board/isee/igep0030/igep0030.c
+++ b/board/isee/igep0030/igep0030.c
@@ -30,27 +30,65 @@
 #include <asm/mach-types.h>
 #include "igep0030.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  * Routine: board_init
  * Description: Early hardware init.
  */
 int board_init(void)
 {
-       DECLARE_GLOBAL_DATA_PTR;
-
        gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
-       /* board id for Linux */
-       gd->bd->bi_arch_number = MACH_TYPE_IGEP0030;
        /* boot param addr */
        gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
 
        return 0;
 }
 
-#ifdef CONFIG_GENERIC_MMC
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: omap_rev_string
+ * Description: For SPL builds output board rev
+ */
+void omap_rev_string(void)
+{
+}
+
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
+                          u32 *mr)
+{
+       *mr = MICRON_V_MR_165;
+#ifdef CONFIG_BOOT_NAND
+       *mcfg = MICRON_V_MCFG_200(256 << 20);
+       *ctrla = MICRON_V_ACTIMA_200;
+       *ctrlb = MICRON_V_ACTIMB_200;
+       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+#else
+       if (get_cpu_family() == CPU_OMAP34XX) {
+               *mcfg = NUMONYX_V_MCFG_165(256 << 20);
+               *ctrla = NUMONYX_V_ACTIMA_165;
+               *ctrlb = NUMONYX_V_ACTIMB_165;
+               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+
+       } else {
+               *mcfg = NUMONYX_V_MCFG_200(256 << 20);
+               *ctrla = NUMONYX_V_ACTIMA_200;
+               *ctrlb = NUMONYX_V_ACTIMB_200;
+               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+       }
+#endif
+}
+#endif
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
-       omap_mmc_init(0);
+       omap_mmc_init(0, 0, 0);
        return 0;
 }
 #endif