EXYNOS5: FDT: Add DWMMC device node data

[oweals/u-boot.git] / board / imx31_phycore / lowlevel_init.S

diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S
index 70f30c0cd942f5fe20e9f87e6872cd5235b1a3fa..4dd78b660a420bcd7785023c203ba0b85e72ff75 100644 (file)
--- a/board/imx31_phycore/lowlevel_init.S
+++ b/board/imx31_phycore/lowlevel_init.S
@@ -21,7 +21,7 @@
  * MA 02111-1307 USA
  */
 
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
 
 .macro REG reg, val
        ldr r2, =\reg
@@ -54,7 +54,7 @@ lowlevel_init:
        REG     CCM_CCMR, 0x074B0BF5 | CCMR_MPE
        REG     CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
 
-       REG     CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
+       REG     CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
 
        REG     CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
 
@@ -63,9 +63,9 @@ lowlevel_init:
        REG     0x43FAC26C, 0 /* SDCLK */
        REG     0x43FAC270, 0 /* CAS */
        REG     0x43FAC274, 0 /* RAS */
-       REG     0x43FAC27C, 0x1000 /* CS2       CSD0) */
+       REG     0x43FAC27C, 0x1000 /* CS2 (CSD0) */
        REG     0x43FAC284, 0 /* DQM3 */
-       REG     0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10       0x288..0x2DC) */
+       REG     0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
        REG     0x43FAC28C, 0
        REG     0x43FAC290, 0
        REG     0x43FAC294, 0