+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Timesys Corporation
* Copyright 2015 General Electric Company
* Copyright 2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
+#include <net.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <i2c.h>
+#include <input.h>
+#include <pwm.h>
+#include <stdlib.h>
+#include "../common/ge_common.h"
+#include "../common/vpd_reader.h"
+#include "../../../drivers/net/e1000.h"
DECLARE_GLOBAL_DATA_PTR;
+struct vpd_cache;
+
+static int confidx = 3; /* Default to b850v3. */
+static struct vpd_cache vpd;
+
+#ifndef CONFIG_SYS_I2C_EEPROM_ADDR
+# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#endif
+
+#ifndef CONFIG_SYS_I2C_EEPROM_BUS
+#define CONFIG_SYS_I2C_EEPROM_BUS 4
+#endif
+
#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_HYS)
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+ gd->ram_size = imx_ddr_size();
return 0;
}
/* Reset AR8033 PHY */
gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
- udelay(500);
+ mdelay(10);
gpio_set_value(IMX_GPIO_NR(1, 28), 1);
+ mdelay(1);
}
static iomux_v3_cfg_t const usdhc2_pads[] = {
/* set debug port address: SerDes Test and System Mode Control */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
/* enable rgmii tx clock delay */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+ /* set the reserved bits to avoid board specific voltage peak issue*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
return 0;
}
/* Backlight enable for LVDS display */
MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
+ /* backlight PWM brightness control */
+ MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void do_enable_hdmi(struct display_info_t const *dev)
return 0;
}
-static int detect_baseboard(struct display_info_t const *dev)
+static int is_b850v3(void)
{
- if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) ||
- IS_ENABLED(CONFIG_TARGET_GE_B650V3))
- return 1;
+ return confidx == 3;
+}
- return 0;
+static int detect_lcd(struct display_info_t const *dev)
+{
+ return !is_b850v3();
}
struct display_info_t const displays[] = {{
.bus = -1,
.addr = -1,
.pixfmt = IPU_PIX_FMT_RGB24,
- .detect = detect_baseboard,
+ .detect = detect_lcd,
.enable = NULL,
.mode = {
.name = "G121X1-L03",
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ enable_videopll();
+
+ /* When a reset/reboot is performed the display power needs to be turned
+ * off for atleast 500ms. The boot time is ~300ms, we need to wait for
+ * an additional 200ms here. Unfortunately we use external PMIC for
+ * doing the reset, so can not differentiate between POR vs soft reset
+ */
+ mdelay(200);
+
/* IPU1 DI0 clock is 480/7 = 68.5 MHz */
setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
return 1;
}
+#define VPD_TYPE_INVALID 0x00
+#define VPD_BLOCK_NETWORK 0x20
+#define VPD_BLOCK_HWID 0x44
+#define VPD_PRODUCT_B850 1
+#define VPD_PRODUCT_B650 2
+#define VPD_PRODUCT_B450 3
+#define VPD_HAS_MAC1 0x1
+#define VPD_HAS_MAC2 0x2
+#define VPD_MAC_ADDRESS_LENGTH 6
+
+struct vpd_cache {
+ u8 product_id;
+ u8 has;
+ unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
+ unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
+};
+
+/*
+ * Extracts MAC and product information from the VPD.
+ */
+static int vpd_callback(void *userdata, u8 id, u8 version, u8 type,
+ size_t size, u8 const *data)
+{
+ struct vpd_cache *vpd = (struct vpd_cache *)userdata;
+
+ if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
+ size >= 1) {
+ vpd->product_id = data[0];
+ } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
+ type != VPD_TYPE_INVALID) {
+ if (size >= 6) {
+ vpd->has |= VPD_HAS_MAC1;
+ memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
+ }
+ if (size >= 12) {
+ vpd->has |= VPD_HAS_MAC2;
+ memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
+ }
+ }
+
+ return 0;
+}
+
+static void process_vpd(struct vpd_cache *vpd)
+{
+ int fec_index = -1;
+ int i210_index = -1;
+
+ switch (vpd->product_id) {
+ case VPD_PRODUCT_B450:
+ env_set("confidx", "1");
+ i210_index = 0;
+ fec_index = 1;
+ break;
+ case VPD_PRODUCT_B650:
+ env_set("confidx", "2");
+ i210_index = 0;
+ fec_index = 1;
+ break;
+ case VPD_PRODUCT_B850:
+ env_set("confidx", "3");
+ i210_index = 1;
+ fec_index = 2;
+ break;
+ }
+
+ if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
+ eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
+
+ if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
+ eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
+}
+
+static int read_vpd(uint eeprom_bus)
+{
+ int res;
+ int size = 1024;
+ uint8_t *data;
+ unsigned int current_i2c_bus = i2c_get_bus_num();
+
+ res = i2c_set_bus_num(eeprom_bus);
+ if (res < 0)
+ return res;
+
+ data = (uint8_t *)malloc(size);
+ if (!data)
+ return -ENOMEM;
+
+ res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ CONFIG_SYS_I2C_EEPROM_ADDR_LEN, data, size);
+
+ if (res == 0) {
+ memset(&vpd, 0, sizeof(vpd));
+ vpd_reader(size, data, &vpd, vpd_callback);
+ }
+
+ free(data);
+
+ i2c_set_bus_num(current_i2c_bus);
+ return res;
+}
+
int board_eth_init(bd_t *bis)
{
setup_iomux_enet();
setup_pcie();
+ e1000_initialize(bis);
+
return cpu_eth_init(bis);
}
MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
+ MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL),
};
#define SUS_S3_OUT IMX_GPIO_NR(4, 11)
#define WIFI_EN IMX_GPIO_NR(6, 14)
setup_iomux_uart();
#if defined(CONFIG_VIDEO_IPUV3)
- if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
+ if (is_b850v3())
/* Set LDB clock to Video PLL */
select_ldb_di_clock_source(MXC_PLL5_CLK);
else
return 0;
}
+static void set_confidx(const struct vpd_cache* vpd)
+{
+ switch (vpd->product_id) {
+ case VPD_PRODUCT_B450:
+ confidx = 1;
+ break;
+ case VPD_PRODUCT_B650:
+ confidx = 2;
+ break;
+ case VPD_PRODUCT_B850:
+ confidx = 3;
+ break;
+ }
+}
+
int board_init(void)
{
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+ setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
+
+ read_vpd(CONFIG_SYS_I2C_EEPROM_BUS);
+
+ set_confidx(&vpd);
+
gpio_direction_output(SUS_S3_OUT, 1);
gpio_direction_output(WIFI_EN, 1);
#if defined(CONFIG_VIDEO_IPUV3)
- if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
+ if (is_b850v3())
setup_display_b850v3();
else
setup_display_bx50v3();
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
- setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
-
return 0;
}
};
#endif
+void pmic_init(void)
+{
+#define I2C_PMIC 0x2
+#define DA9063_I2C_ADDR 0x58
+#define DA9063_REG_BCORE2_CFG 0x9D
+#define DA9063_REG_BCORE1_CFG 0x9E
+#define DA9063_REG_BPRO_CFG 0x9F
+#define DA9063_REG_BIO_CFG 0xA0
+#define DA9063_REG_BMEM_CFG 0xA1
+#define DA9063_REG_BPERI_CFG 0xA2
+#define DA9063_BUCK_MODE_MASK 0xC0
+#define DA9063_BUCK_MODE_MANUAL 0x00
+#define DA9063_BUCK_MODE_SLEEP 0x40
+#define DA9063_BUCK_MODE_SYNC 0x80
+#define DA9063_BUCK_MODE_AUTO 0xC0
+
+ uchar val;
+
+ i2c_set_bus_num(I2C_PMIC);
+
+ i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
+ val &= ~DA9063_BUCK_MODE_MASK;
+ val |= DA9063_BUCK_MODE_SYNC;
+ i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
+
+ i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
+ val &= ~DA9063_BUCK_MODE_MASK;
+ val |= DA9063_BUCK_MODE_SYNC;
+ i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
+
+ i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
+ val &= ~DA9063_BUCK_MODE_MASK;
+ val |= DA9063_BUCK_MODE_SYNC;
+ i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
+
+ i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
+ val &= ~DA9063_BUCK_MODE_MASK;
+ val |= DA9063_BUCK_MODE_SYNC;
+ i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
+
+ i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
+ val &= ~DA9063_BUCK_MODE_MASK;
+ val |= DA9063_BUCK_MODE_SYNC;
+ i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
+
+ i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
+ val &= ~DA9063_BUCK_MODE_MASK;
+ val |= DA9063_BUCK_MODE_SYNC;
+ i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
+}
+
int board_late_init(void)
{
+ process_vpd(&vpd);
+
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
- /* We need at least 200ms between power on and backlight on
- * as per specifications from CHI MEI */
- mdelay(250);
- /* Backlight Power */
- gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
+ if (is_b850v3())
+ env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
+
+ /* board specific pmic init */
+ pmic_init();
+
+ check_time();
+
+ return 0;
+}
+
+/*
+ * Removes the 'eth[0-9]*addr' environment variable with the given index
+ *
+ * @param index [in] the index of the eth_device whose variable is to be removed
+ */
+static void remove_ethaddr_env_var(int index)
+{
+ char env_var_name[9];
+
+ sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
+ env_set(env_var_name, NULL);
+}
+
+int last_stage_init(void)
+{
+ int i;
+
+ /*
+ * Remove first three ethaddr which may have been created by
+ * function process_vpd().
+ */
+ for (i = 0; i < 3; ++i)
+ remove_ethaddr_env_var(i);
return 0;
}
printf("BOARD: %s\n", CONFIG_BOARD_NAME);
return 0;
}
+
+static int do_backlight_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+#ifdef CONFIG_VIDEO_IPUV3
+ /* We need at least 200ms between power on and backlight on
+ * as per specifications from CHI MEI */
+ mdelay(250);
+
+ /* enable backlight PWM 1 */
+ pwm_init(0, 0, 0);
+
+ /* duty cycle 5000000ns, period: 5000000ns */
+ pwm_config(0, 5000000, 5000000);
+
+ /* Backlight Power */
+ gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
+
+ pwm_enable(0);
+#endif
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ bx50_backlight_enable, 1, 1, do_backlight_enable,
+ "enable Bx50 backlight",
+ ""
+);