#include <miiphy.h>
-#include "../common/fpga.h"
+#include <gdsys_fpga.h>
#define PHYREG_CONTROL 0
#define PHYREG_PAGE_ADDRESS 22
#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
-enum {
- REG_VERSIONS = 0x0002,
- REG_FPGA_FEATURES = 0x0004,
- REG_FPGA_VERSION = 0x0006,
- REG_QUAD_SERDES_RESET = 0x0012,
-};
-
enum {
UNITTYPE_CCD_SWITCH = 1,
};
*/
int checkboard(void)
{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
char *s = getenv("serial#");
- u16 versions = fpga_get_reg(REG_VERSIONS);
- u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
- u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+ u16 versions = in_le16(&fpga->versions);
+ u16 fpga_version = in_le16(&fpga->fpga_version);
+ u16 fpga_features = in_le16(&fpga->fpga_features);
unsigned unit_type;
unsigned hardware_version;
unsigned feature_channels;
*/
int last_stage_init(void)
{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
unsigned int k;
miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
configure_gbit_phy(k);
/* take fpga serdes blocks out of reset */
- fpga_set_reg(REG_QUAD_SERDES_RESET, 0);
+ out_le16(&fpga->quad_serdes_reset, 0);
return 0;
}