imx: ventana: remove 128x16 calibration (share with 128x32)

[oweals/u-boot.git] / board / gateworks / gw_ventana / gw_ventana_spl.c

diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index ca35b3cb7ec8b251b8a7dba127041092b36823d8..b839b8900f223d37ddceb765568c63a0abe8c262 100644 (file)
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -8,6 +8,7 @@
 #include <common.h>
 #include <i2c.h>
 #include <asm/io.h>
+#include <asm/arch/crm_regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-ddr.h>
 #include <asm/arch/mx6-pins.h>
@@ -187,7 +188,7 @@ struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
        .grp_b7ds = 0x00000030,
 };
 
-/* MT41K128M16JT-125 */
+/* MT41K128M16JT-125 (2Gb density) */
 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
        .mem_speed = 1600,
        .density = 2,
@@ -201,7 +202,7 @@ static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
        .trasmin = 3500,
 };
 
-/* MT41K256M16HA-125 */
+/* MT41K256M16HA-125 (4Gb density) */
 static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
        .mem_speed = 1600,
        .density = 4,
@@ -219,6 +220,32 @@ static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
  * calibration - these are the various CPU/DDR3 combinations we support
  */
 
+static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
+       /* write leveling calibration determine */
+       .p0_mpwldectrl0 = 0x001B0016,
+       .p0_mpwldectrl1 = 0x000C000E,
+       /* Read DQS Gating calibration */
+       .p0_mpdgctrl0 = 0x4324033A,
+       .p0_mpdgctrl1 = 0x00000000,
+       /* Read Calibration: DQS delay relative to DQ read access */
+       .p0_mprddlctl = 0x40403438,
+       /* Write Calibration: DQ/DM delay relative to DQS write access */
+       .p0_mpwrdlctl = 0x40403D36,
+};
+
+static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
+       /* write leveling calibration determine */
+       .p0_mpwldectrl0 = 0x00420043,
+       .p0_mpwldectrl1 = 0x0016001A,
+       /* Read DQS Gating calibration */
+       .p0_mpdgctrl0 = 0x4238023B,
+       .p0_mpdgctrl1 = 0x00000000,
+       /* Read Calibration: DQS delay relative to DQ read access */
+       .p0_mprddlctl = 0x40404849,
+       /* Write Calibration: DQ/DM delay relative to DQS write access */
+       .p0_mpwrdlctl = 0x40402E2F,
+};
+
 static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
        /* write leveling calibration determine */
        .p0_mpwldectrl0 = 0x00190017,
@@ -296,6 +323,19 @@ static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
        .p0_mpwrdlctl = 0x32363934,
 };
 
+static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
+       /* write leveling calibration determine */
+       .p0_mpwldectrl0 = 0X00480047,
+       .p0_mpwldectrl1 = 0X003D003F,
+       /* Read DQS Gating calibration */
+       .p0_mpdgctrl0 = 0X423E0241,
+       .p0_mpdgctrl1 = 0X022B022C,
+       /* Read Calibration: DQS delay relative to DQ read access */
+       .p0_mprddlctl = 0X49454A4A,
+       /* Write Calibration: DQ/DM delay relative to DQS write access */
+       .p0_mpwrdlctl = 0X2E372C32,
+};
+
 static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
        /* write leveling calibration determine */
        .p0_mpwldectrl0 = 0X00220021,
@@ -339,6 +379,7 @@ static void spl_dram_init(int width, int size_mb, int board_model)
                .bi_on = 1,     /* Bank interleaving enabled */
                .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
                .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
+               .pd_fast_exit = 1, /* enable precharge power-down fast exit */
        };
 
        /*
@@ -348,7 +389,22 @@ static void spl_dram_init(int width, int size_mb, int board_model)
         *   mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
         *   mx6_ddr_cfg - chip specific timing/layout details
         */
-       if (width == 32 && size_mb == 512) {
+       if (width == 16 && size_mb == 256) {
+               /* 1x 2Gb density chip - same calib as 2x 2Gb */
+               mem = &mt41k128m16jt_125;
+               if (is_cpu_type(MXC_CPU_MX6Q))
+                       calib = &mx6dq_128x32_mmdc_calib;
+               else
+                       calib = &mx6sdl_128x32_mmdc_calib;
+               debug("2gB density\n");
+       } else if (width == 16 && size_mb == 512) {
+               mem = &mt41k256m16ha_125;
+               if (is_cpu_type(MXC_CPU_MX6Q))
+                       calib = &mx6dq_256x16_mmdc_calib;
+               else
+                       calib = &mx6sdl_256x16_mmdc_calib;
+               debug("4gB density\n");
+       } else if (width == 32 && size_mb == 512) {
                mem = &mt41k128m16jt_125;
                if (is_cpu_type(MXC_CPU_MX6Q))
                        calib = &mx6dq_128x32_mmdc_calib;
@@ -366,6 +422,8 @@ static void spl_dram_init(int width, int size_mb, int board_model)
                mem = &mt41k256m16ha_125;
                if (is_cpu_type(MXC_CPU_MX6Q))
                        calib = &mx6dq_256x32_mmdc_calib;
+               else
+                       calib = &mx6sdl_256x32_mmdc_calib;
                debug("4gB density\n");
        } else if (width == 64 && size_mb == 2048) {
                mem = &mt41k256m16ha_125;
@@ -392,6 +450,30 @@ static void spl_dram_init(int width, int size_mb, int board_model)
        mx6_dram_cfg(&sysinfo, calib, mem);
 }
 
+static void ccgr_init(void)
+{
+       struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+       writel(0x00C03F3F, &ccm->CCGR0);
+       writel(0x0030FC03, &ccm->CCGR1);
+       writel(0x0FFFC000, &ccm->CCGR2);
+       writel(0x3FF00000, &ccm->CCGR3);
+       writel(0xFFFFF300, &ccm->CCGR4);        /* enable NAND/GPMI/BCH clks */
+       writel(0x0F0000C3, &ccm->CCGR5);
+       writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+       struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+       /* enable AXI cache for VDOA/VPU/IPU */
+       writel(0xF00000CF, &iomux->gpr[4]);
+       /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+       writel(0x007F007F, &iomux->gpr[6]);
+       writel(0x007F007F, &iomux->gpr[7]);
+}
+
 /*
  * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
  * - we have a stack and a place to store GD, both in SRAM
@@ -405,6 +487,9 @@ void board_init_f(ulong dummy)
        /* setup AIPS and disable watchdog */
        arch_cpu_init();
 
+       ccgr_init();
+       gpr_init();
+
        /* iomux and setup of i2c */
        board_early_init_f();
        i2c_setup_iomux();