#include <common.h>
#include <i2c.h>
#include <asm/io.h>
+#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
.grp_b7ds = 0x00000030,
};
-/* MT41K128M16JT-125 */
+/* MT41K64M16JT-125 (1Gb density) */
+static struct mx6_ddr3_cfg mt41k64m16jt_125 = {
+ .mem_speed = 1600,
+ .density = 1,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 13,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+/* MT41K128M16JT-125 (2Gb density) */
static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
.mem_speed = 1600,
.density = 2,
.trasmin = 3500,
};
-/* GW54xx specific calibration */
-static struct mx6_mmdc_calibration gw54xxq_mmdc_calib = {
+/* MT41K256M16HA-125 (4Gb density) */
+static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
+ .mem_speed = 1600,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+/*
+ * calibration - these are the various CPU/DDR3 combinations we support
+ */
+static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
/* write leveling calibration determine */
- .p0_mpwldectrl0 = 0x00190018,
- .p0_mpwldectrl1 = 0x0021001D,
- .p1_mpwldectrl0 = 0x00160027,
- .p1_mpwldectrl1 = 0x0012001E,
+ .p0_mpwldectrl0 = 0x004C004E,
+ .p0_mpwldectrl1 = 0x00440044,
/* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x43370346,
- .p0_mpdgctrl1 = 0x032A0321,
- .p1_mpdgctrl0 = 0x433A034D,
- .p1_mpdgctrl1 = 0x032F0235,
+ .p0_mpdgctrl0 = 0x42440247,
+ .p0_mpdgctrl1 = 0x02310232,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x45424746,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x33382C31,
+};
+
+static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x001B0016,
+ .p0_mpwldectrl1 = 0x000C000E,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x4324033A,
+ .p0_mpdgctrl1 = 0x00000000,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x40403438,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x40403D36,
+};
+
+static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x00420043,
+ .p0_mpwldectrl1 = 0x0016001A,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x4238023B,
+ .p0_mpdgctrl1 = 0x00000000,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x40404849,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x40402E2F,
+};
+
+static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x00190017,
+ .p0_mpwldectrl1 = 0x00140026,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x43380347,
+ .p0_mpdgctrl1 = 0x433C034D,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x3C313539,
- .p1_mprddlctl = 0x37333140,
/* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0x37393C38,
- .p1_mpwrdlctl = 0x42334538,
+ .p0_mpwrdlctl = 0x36393C39,
};
-/* GW53xx specific calibration */
-static struct mx6_mmdc_calibration gw53xxq_mmdc_calib = {
+static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
/* write leveling calibration determine */
- .p0_mpwldectrl0 = 0x00160013,
- .p0_mpwldectrl1 = 0x00090024,
- .p1_mpwldectrl0 = 0x001F0018,
- .p1_mpwldectrl1 = 0x000C001C,
+ .p0_mpwldectrl0 = 0x003C003C,
+ .p0_mpwldectrl1 = 0x001F002A,
/* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x433A034C,
- .p0_mpdgctrl1 = 0x0336032F,
- .p1_mpdgctrl0 = 0x4343034A,
- .p1_mpdgctrl1 = 0x03370222,
+ .p0_mpdgctrl0 = 0x42410244,
+ .p0_mpdgctrl1 = 0x4234023A,
/* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0x3F343638,
- .p1_mprddlctl = 0x38373442,
+ .p0_mprddlctl = 0x484A4C4B,
/* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0x343A3E39,
- .p1_mpwrdlctl = 0x44344239,
+ .p0_mpwrdlctl = 0x33342B32,
};
-static struct mx6_mmdc_calibration gw53xxdl_mmdc_calib = {
+
+static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x00190017,
+ .p0_mpwldectrl1 = 0x00140026,
+ .p1_mpwldectrl0 = 0x0021001C,
+ .p1_mpwldectrl1 = 0x0011001D,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x43380347,
+ .p0_mpdgctrl1 = 0x433C034D,
+ .p1_mpdgctrl0 = 0x032C0324,
+ .p1_mpdgctrl1 = 0x03310232,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x3C313539,
+ .p1_mprddlctl = 0x37343141,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x36393C39,
+ .p1_mpwrdlctl = 0x42344438,
+};
+
+static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
/* write leveling calibration determine */
.p0_mpwldectrl0 = 0x003C003C,
- .p0_mpwldectrl1 = 0x00330038,
- .p1_mpwldectrl0 = 0x001F002A,
+ .p0_mpwldectrl1 = 0x001F002A,
+ .p1_mpwldectrl0 = 0x00330038,
.p1_mpwldectrl1 = 0x0022003F,
/* Read DQS Gating calibration */
.p0_mpdgctrl0 = 0x42410244,
- .p0_mpdgctrl1 = 0x022D022D,
- .p1_mpdgctrl0 = 0x4234023A,
+ .p0_mpdgctrl1 = 0x4234023A,
+ .p1_mpdgctrl0 = 0x022D022D,
.p1_mpdgctrl1 = 0x021C0228,
/* Read Calibration: DQS delay relative to DQ read access */
.p0_mprddlctl = 0x484A4C4B,
.p1_mpwrdlctl = 0x3933332B,
};
-/* GW52xx specific calibration */
-static struct mx6_mmdc_calibration gw52xxdl_mmdc_calib = {
+static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
/* write leveling calibration determine */
- .p0_mpwldectrl0 = 0x0040003F,
- .p0_mpwldectrl1 = 0x00370037,
+ .p0_mpwldectrl0 = 0x001E001A,
+ .p0_mpwldectrl1 = 0x0026001F,
/* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x42420244,
- .p0_mpdgctrl1 = 0x022F022F,
+ .p0_mpdgctrl0 = 0x43370349,
+ .p0_mpdgctrl1 = 0x032D0327,
/* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0x49464B4A,
+ .p0_mprddlctl = 0x3D303639,
/* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0x32362C32,
+ .p0_mpwrdlctl = 0x32363934,
};
-/* GW51xx specific calibration */
-static struct mx6_mmdc_calibration gw51xxq_mmdc_calib = {
+static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
/* write leveling calibration determine */
- .p0_mpwldectrl0 = 0x00150016,
- .p0_mpwldectrl1 = 0x001F0017,
+ .p0_mpwldectrl0 = 0X00480047,
+ .p0_mpwldectrl1 = 0X003D003F,
/* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x433D034D,
- .p0_mpdgctrl1 = 0x033D032F,
+ .p0_mpdgctrl0 = 0X423E0241,
+ .p0_mpdgctrl1 = 0X022B022C,
/* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0x3F313639,
+ .p0_mprddlctl = 0X49454A4A,
/* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0x33393F36,
+ .p0_mpwrdlctl = 0X2E372C32,
};
-static struct mx6_mmdc_calibration gw51xxdl_mmdc_calib = {
+static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
/* write leveling calibration determine */
- .p0_mpwldectrl0 = 0x003D003F,
- .p0_mpwldectrl1 = 0x002F0038,
+ .p0_mpwldectrl0 = 0X00220021,
+ .p0_mpwldectrl1 = 0X00200030,
+ .p1_mpwldectrl0 = 0X002D0027,
+ .p1_mpwldectrl1 = 0X00150026,
/* Read DQS Gating calibration */
- .p0_mpdgctrl0 = 0x423A023A,
- .p0_mpdgctrl1 = 0x022A0228,
+ .p0_mpdgctrl0 = 0x43330342,
+ .p0_mpdgctrl1 = 0x0339034A,
+ .p1_mpdgctrl0 = 0x032F0325,
+ .p1_mpdgctrl1 = 0x032F022E,
/* Read Calibration: DQS delay relative to DQ read access */
- .p0_mprddlctl = 0x48494C4C,
+ .p0_mprddlctl = 0X3A2E3437,
+ .p1_mprddlctl = 0X35312F3F,
/* Write Calibration: DQ/DM delay relative to DQS write access */
- .p0_mpwrdlctl = 0x34352D31,
+ .p0_mpwrdlctl = 0X33363B37,
+ .p1_mpwrdlctl = 0X40304239,
};
-static void spl_dram_init(int width, int size, int board_model)
+static void spl_dram_init(int width, int size_mb, int board_model)
{
- struct mx6_ddr3_cfg *mem = &mt41k128m16jt_125;
- struct mx6_mmdc_calibration *calib;
+ struct mx6_ddr3_cfg *mem = NULL;
+ struct mx6_mmdc_calibration *calib = NULL;
struct mx6_ddr_sysinfo sysinfo = {
/* width of data bus:0=16,1=32,2=64 */
.dsize = width/32,
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ .pd_fast_exit = 1, /* enable precharge power-down fast exit */
};
/*
* MMDC Calibration requires the following data:
* mx6_mmdc_calibration - board-specific calibration (routing delays)
+ * these calibration values depend on board routing, SoC, and DDR
* mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
* mx6_ddr_cfg - chip specific timing/layout details
*/
- switch (board_model) {
- default:
- case GW51xx:
+ if (width == 16 && size_mb == 128) {
+ mem = &mt41k64m16jt_125;
if (is_cpu_type(MXC_CPU_MX6Q))
- calib = &gw51xxq_mmdc_calib;
+ ;
else
- calib = &gw51xxdl_mmdc_calib;
- break;
- case GW52xx:
- calib = &gw52xxdl_mmdc_calib;
- break;
- case GW53xx:
+ calib = &mx6sdl_64x16_mmdc_calib;
+ debug("1gB density\n");
+ } else if (width == 16 && size_mb == 256) {
+ /* 1x 2Gb density chip - same calib as 2x 2Gb */
+ mem = &mt41k128m16jt_125;
if (is_cpu_type(MXC_CPU_MX6Q))
- calib = &gw53xxq_mmdc_calib;
+ calib = &mx6dq_128x32_mmdc_calib;
else
- calib = &gw53xxdl_mmdc_calib;
- break;
- case GW54xx:
- calib = &gw54xxq_mmdc_calib;
- break;
+ calib = &mx6sdl_128x32_mmdc_calib;
+ debug("2gB density\n");
+ } else if (width == 16 && size_mb == 512) {
+ mem = &mt41k256m16ha_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &mx6dq_256x16_mmdc_calib;
+ else
+ calib = &mx6sdl_256x16_mmdc_calib;
+ debug("4gB density\n");
+ } else if (width == 32 && size_mb == 256) {
+ /* Same calib as width==16, size==128 */
+ mem = &mt41k64m16jt_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ ;
+ else
+ calib = &mx6sdl_64x16_mmdc_calib;
+ debug("1gB density\n");
+ } else if (width == 32 && size_mb == 512) {
+ mem = &mt41k128m16jt_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &mx6dq_128x32_mmdc_calib;
+ else
+ calib = &mx6sdl_128x32_mmdc_calib;
+ debug("2gB density\n");
+ } else if (width == 32 && size_mb == 1024) {
+ mem = &mt41k256m16ha_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &mx6dq_256x32_mmdc_calib;
+ else
+ calib = &mx6sdl_256x32_mmdc_calib;
+ debug("4gB density\n");
+ } else if (width == 64 && size_mb == 512) {
+ mem = &mt41k64m16jt_125;
+ debug("1gB density\n");
+ } else if (width == 64 && size_mb == 1024) {
+ mem = &mt41k128m16jt_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &mx6dq_128x64_mmdc_calib;
+ else
+ calib = &mx6sdl_128x64_mmdc_calib;
+ debug("2gB density\n");
+ } else if (width == 64 && size_mb == 2048) {
+ mem = &mt41k256m16ha_125;
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &mx6dq_256x64_mmdc_calib;
+ debug("4gB density\n");
+ }
+
+ if (!(mem && calib)) {
+ puts("Error: Invalid Calibration/Board Configuration\n");
+ printf("MEM : %s\n", mem ? "OKAY" : "NULL");
+ printf("CALIB : %s\n", calib ? "OKAY" : "NULL");
+ printf("CPUTYPE: %s\n",
+ is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL");
+ printf("SIZE_MB: %d\n", size_mb);
+ printf("WIDTH : %d\n", width);
+ hang();
}
if (is_cpu_type(MXC_CPU_MX6Q))
mx6_dram_cfg(&sysinfo, calib, mem);
}
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+}
+
/*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
struct ventana_board_info ventana_info;
int board_model;
- /*
- * Zero out global data:
- * - this shoudl be done by crt0.S
- * - failure to zero it will cause i2c_setup to fail
- */
- memset((void *)gd, 0, sizeof(struct global_data));
+ /* setup clock gating */
+ ccgr_init();
/* setup AIPS and disable watchdog */
arch_cpu_init();
+ /* setup AXI */
+ gpr_init();
+
/* iomux and setup of i2c */
board_early_init_f();
i2c_setup_iomux();
board_init_r(NULL, 0);
}
+/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
+/* its our chance to print info about boot device */
+void spl_board_init(void)
+{
+ /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
+ u32 boot_device = spl_boot_device();
+
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ puts("Booting from MMC\n");
+ break;
+ case BOOT_DEVICE_NAND:
+ puts("Booting from NAND\n");
+ break;
+ case BOOT_DEVICE_SATA:
+ puts("Booting from SATA\n");
+ break;
+ default:
+ puts("Unknown boot device\n");
+ }
+}
+
void reset_cpu(ulong addr)
{
}
projects / oweals / u-boot.git / blobdiff